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[213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442f33690f0sm102074085e9.1.2025.05.16.04.38.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 May 2025 04:38:00 -0700 (PDT) Message-ID: Date: Fri, 16 May 2025 12:37:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] hw/intc/arm_gic: introduce a first-cpu-index property To: =?UTF-8?Q?Cl=C3=A9ment_Chigot?= Cc: qemu-devel@nongnu.org, Pierrick Bouvier , qemu-arm@nongnu.org, peter.maydell@linaro.org, edgar.iglesias@gmail.com, alistair@alistair23.me, Frederic Konrad References: <20250513141448.297946-1-chigot@adacore.com> <20250513141448.297946-3-chigot@adacore.com> <3314f721-9c5e-479b-9fcc-3b8a021efde9@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Clément, On 14/5/25 14:41, Clément Chigot wrote: > On Tue, May 13, 2025 at 5:39 PM Philippe Mathieu-Daudé > wrote: >> >> On 13/5/25 16:14, Clément Chigot wrote: >>> From: Frederic Konrad >>> >>> This introduces a first-cpu-index property to the arm-gic, as some SOCs >>> could have two separate GIC (ie: the zynqmp). >>> >>> Signed-off-by: Clément Chigot >>> --- >>> hw/intc/arm_gic.c | 2 +- >>> hw/intc/arm_gic_common.c | 1 + >>> include/hw/intc/arm_gic_common.h | 2 ++ >>> 3 files changed, 4 insertions(+), 1 deletion(-) >>> >>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >>> index d18bef40fc..899f133363 100644 >>> --- a/hw/intc/arm_gic.c >>> +++ b/hw/intc/arm_gic.c >>> @@ -59,7 +59,7 @@ static const uint8_t gic_id_gicv2[] = { >>> static inline int gic_get_current_cpu(GICState *s) >>> { >>> if (!qtest_enabled() && s->num_cpu > 1) { >>> - return current_cpu->cpu_index; >>> + return current_cpu->cpu_index - s->first_cpu_index; >> >> Note, CPUState::cpu_index is meant for accelerators code and shouldn't >> be used in hw/ (in particular because it vary when using hotplug). > > Is there another way to perform that then ? As you can see `cpu_index` > is already present prior to my patch. I don't mind improving it as a > prerequisite for that series though. Yeah it is a pre-existing design issue, I was just thinking loudly, no need to worry for your use: if we ever clean it, we'll also clean here. > >>> } >>> return 0; >>> } >>> diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c >>> index 0f0c48d89a..ed5be05645 100644 >>> --- a/hw/intc/arm_gic_common.c >>> +++ b/hw/intc/arm_gic_common.c >>> @@ -350,6 +350,7 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, >>> >>> static const Property arm_gic_common_properties[] = { >>> DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), >>> + DEFINE_PROP_UINT32("first-cpu-index", GICState, first_cpu_index, 0), >>> DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), >>> /* Revision can be 1 or 2 for GIC architecture specification >>> * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. >>> diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h >>> index 97fea4102d..93a3cc2bf8 100644 >>> --- a/include/hw/intc/arm_gic_common.h >>> +++ b/include/hw/intc/arm_gic_common.h >>> @@ -129,6 +129,8 @@ struct GICState { >>> uint32_t num_lrs; >>> >>> uint32_t num_cpu; >>> + /* cpu_index of the first CPU, attached to this GIC. */ >>> + uint32_t first_cpu_index; >>> >>> MemoryRegion iomem; /* Distributor */ >>> /* This is just so we can have an opaque pointer which identifies >> >> Alternative series motivated to remove &first_cpu / qemu_get_cpu(): >> https://lore.kernel.org/qemu-devel/20231212162935.42910-1-philmd@linaro.org/ (Just an observation, not an objection to this simple work-around). Regards, Phil.