Re: [PATCH-for-10.1 v3 7/9] hw/arm/virt-acpi: Always build IORT table (even with GIC ITS disabled)

[Gustavo Romero <gustavo.romero@linaro.org>]

Hi Phil,

On 4/3/25 17:40, Philippe Mathieu-Daudé wrote:
> Citing Gustavo [*]:
> 
>    Gating IORT table generation entirely based on the presence
>    of ITS looks wrong because IORT table has data beyond GIC ITS,
>    like for SMMUv3 etc..
> 
> [*] https://lore.kernel.org/qemu-devel/bae6e29a-7290-47d2-8caf-14702ee091f0@linaro.org/
> 
> Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Maybe it's worth to cite the "IO Remapping Table Platform Design Document",
in particular page 10, which reads:

"the IORT provides an ACPI description for IO topology, SMMUs, and GIC ITSs"

https://developer.arm.com/documentation/den0049/latest/

Now that the target is 10.1, let me thing a bit more about it.


Cheers,
Gustavo

> ---
>   hw/arm/virt-acpi-build.c | 38 +++++++++++++++++++++-----------------
>   1 file changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 1c389ef5cdb..e7e27951cb9 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -287,6 +287,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>       uint32_t id = 0;
>       GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
>       GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
> +    bool has_its = its_enabled(vms);
>   
>       AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
>                           .oem_table_id = vms->oem_table_id };
> @@ -325,9 +326,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>   
>           nb_nodes = 3; /* RC, ITS, SMMUv3 */
>           rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
> -    } else {
> +    } else if (has_its) {
>           nb_nodes = 2; /* RC, ITS */
>           rc_mapping_count = 1;
> +    } else {
> +        nb_nodes = 1; /* RC */
> +        rc_mapping_count = 1;
>       }
>       /* Number of IORT Nodes */
>       build_append_int_noprefix(table_data, nb_nodes, 4);
> @@ -336,17 +340,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>       build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
>       build_append_int_noprefix(table_data, 0, 4); /* Reserved */
>   
> -    /* Table 12 ITS Group Format */
> -    build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
> -    node_size =  20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
> -    build_append_int_noprefix(table_data, node_size, 2); /* Length */
> -    build_append_int_noprefix(table_data, 1, 1); /* Revision */
> -    build_append_int_noprefix(table_data, id++, 4); /* Identifier */
> -    build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
> -    build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
> -    build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
> -    /* GIC ITS Identifier Array */
> -    build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
> +    if (has_its) {
> +        /* Table 12 ITS Group Format */
> +        build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ //
> +        node_size =  20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
> +        build_append_int_noprefix(table_data, node_size, 2); /* Length */
> +        build_append_int_noprefix(table_data, 1, 1); /* Revision */
> +        build_append_int_noprefix(table_data, id++, 4); /* Identifier */
> +        build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
> +        build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
> +        build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
> +        /* GIC ITS Identifier Array */
> +        build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
> +    }
>   
>       if (vms->iommu == VIRT_IOMMU_SMMUV3) {
>           int irq =  vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
> @@ -429,7 +435,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>               build_iort_id_mapping(table_data, range->input_base,
>                                     range->id_count, IORT_NODE_OFFSET);
>           }
> -    } else {
> +    } else if (has_its) {
>           /* output IORT node is the ITS group node (the first node) */
>           build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
>       }
> @@ -979,10 +985,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
>                             vms->oem_table_id);
>       }
>   
> -    if (its_enabled(vms)) {
> -        acpi_add_table(table_offsets, tables_blob);
> -        build_iort(tables_blob, tables->linker, vms);
> -    }
> +    acpi_add_table(table_offsets, tables_blob);
> +    build_iort(tables_blob, tables->linker, vms);
>   
>   #ifdef CONFIG_TPM
>       if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {