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From: Paolo Bonzini <pbonzini@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] target/i386: fix cmpxchg with 32-bit register destination
Date: Thu, 15 Sep 2022 01:50:25 +0200	[thread overview]
Message-ID: <ed0fa748-5560-9ea5-ea06-bc8213b9942f@redhat.com> (raw)
In-Reply-To: <91fe80d5-724b-6adc-ef74-60655c8a25cf@linaro.org>

On 9/12/22 09:55, Richard Henderson wrote:
> 
>   * Compute...
> 
> Why bother passing NULL, and fixing it up at each use...
> 
>> +static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv 
>> t0)
>> +{
>> +    gen_op_deposit_reg_v(s, ot, reg, NULL, t0);
>>   }
> 
> ... when you can just as easily pass in the register here?

Because dest can be fixed up to either cpu_regs[reg - 4] for high-byte 
registers, or cpu_regs[reg] for everything else.

> We have an outstanding bug report that suggests that the move to eax must use the deposit in both cases:
> 
> https://gitlab.com/qemu-project/qemu/-/issues/508

Ok, so that's two bugs.  But both of them can indeed be fixed with 
gen_op_deposit_reg_v.

Paolo



  reply	other threads:[~2022-09-14 23:52 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-11 22:26 [PATCH 0/2] target/i386: two fixes for cmpxchg Paolo Bonzini
2022-09-11 22:26 ` [PATCH 1/2] target/i386: fix cmpxchg with 32-bit register destination Paolo Bonzini
2022-09-12  7:55   ` Richard Henderson
2022-09-14 23:50     ` Paolo Bonzini [this message]
2022-09-11 22:26 ` [PATCH 2/2] target/i386: cmpxchg only overwrites ZF Paolo Bonzini
2022-09-12  7:58   ` Richard Henderson

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