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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5c4c0321sm28255545e9.8.2025.10.01.00.38.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Oct 2025 00:38:51 -0700 (PDT) Message-ID: Date: Wed, 1 Oct 2025 09:38:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/33] target/riscv: Fix size of mhartid Content-Language: en-US To: Anton Johansson , qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com References: <20251001073306.28573-1-anjo@rev.ng> <20251001073306.28573-4-anjo@rev.ng> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251001073306.28573-4-anjo@rev.ng> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/10/25 09:32, Anton Johansson wrote: > and update formatting in log. > > Signed-off-by: Anton Johansson > --- > target/riscv/cpu.h | 2 +- > target/riscv/cpu_helper.c | 2 +- > target/riscv/machine.c | 2 +- > target/riscv/tcg/tcg-cpu.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 736e4f6daa..3235108112 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -279,7 +279,7 @@ struct CPUArchState { > target_ulong geilen; > uint64_t resetvec; > > - target_ulong mhartid; > + uint64_t mhartid; > /* > * For RV32 this is 32-bit mstatus and 32-bit mstatush. > * For RV64 this is a 64-bit mstatus. > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 99e46c3136..328fb674e1 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -425,7 +425,7 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINTTL(env.priv, RISCVCPU), > VMSTATE_BOOL(env.virt_enabled, RISCVCPU), > VMSTATE_UINT64(env.resetvec, RISCVCPU), > - VMSTATE_UINTTL(env.mhartid, RISCVCPU), > + VMSTATE_UINT64(env.mhartid, RISCVCPU), The problem is you break the migration stream again. Maybe simpler to just squash with previous patch? Thay said, IIUC mhartid is only set once in riscv_hart_realize(). I suspect it is pointless to migrate it.