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([2602:ae:1547:e101:4ae9:ceee:85cc:a70c]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c2ca00b0015e8d4eb207sm11135734pla.81.2022.05.31.07.36.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 May 2022 07:36:02 -0700 (PDT) Message-ID: Date: Tue, 31 May 2022 07:36:00 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] target/arm: Declare support for FEAT_RASv1p1 Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220531114258.855804-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220531114258.855804-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/31/22 04:42, Peter Maydell wrote: > The architectural feature RASv1p1 introduces the following new > features: > * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 > * new bits in the fine-grained trap registers that control traps > for these new registers > * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps > for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 > * a larger number of the ERXMISC_EL1 registers > * the format of ERRSTATUS registers changes > > The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for > QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN > and SCR_EL3.FIEN bits may be RES0. We don't have any ERRSTATUS > registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet > implement the fine-grained-trap extension. So there is nothing we > need to implement to be compliant with the feature spec. Make the > 'max' CPU report the feature in its ID registers, and document it. > > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson r~