* [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common chiplet model
2023-11-27 17:13 [PATCH v6 0/3] pnv nest1 chiplet model Chalapathi V
@ 2023-11-27 17:13 ` Chalapathi V
2023-11-28 2:04 ` Nicholas Piggin
2023-11-28 14:24 ` Cédric Le Goater
2023-11-27 17:13 ` [PATCH v6 2/3] hw/ppc: Add N1 " Chalapathi V
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: Chalapathi V @ 2023-11-27 17:13 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, clg, calebs, chalapathi.v,
chalapathi.v, saif.abrar
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets have a common basic set of registers and This model will provide
the registers functionality for common registers of nest chiplet (Pervasive
Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
This commit implement the read/write functions of chiplet control registers.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
---
include/hw/ppc/pnv_nest_pervasive.h | 36 +++++
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++
hw/ppc/meson.build | 1 +
4 files changed, 259 insertions(+)
create mode 100644 include/hw/ppc/pnv_nest_pervasive.h
create mode 100644 hw/ppc/pnv_nest_pervasive.c
diff --git a/include/hw/ppc/pnv_nest_pervasive.h b/include/hw/ppc/pnv_nest_pervasive.h
new file mode 100644
index 0000000000..9f11531f52
--- /dev/null
+++ b/include/hw/ppc/pnv_nest_pervasive.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU PowerPC nest pervasive common chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_PNV_NEST_PERVASIVE_H
+#define PPC_PNV_NEST_PERVASIVE_H
+
+#define TYPE_PNV_NEST_PERVASIVE "pnv-nest-chiplet-pervasive"
+#define PNV_NEST_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_PERVASIVE)
+
+typedef struct PnvPervasiveCtrlRegs {
+#define CPLT_CTRL_SIZE 6
+ uint64_t cplt_ctrl[CPLT_CTRL_SIZE];
+ uint64_t cplt_cfg0;
+ uint64_t cplt_cfg1;
+ uint64_t cplt_stat0;
+ uint64_t cplt_mask0;
+ uint64_t ctrl_protect_mode;
+ uint64_t ctrl_atomic_lock;
+} PnvPervasiveCtrlRegs;
+
+typedef struct PnvNestChipletPervasive {
+ DeviceState parent;
+ char *parent_obj_name;
+ MemoryRegion xscom_ctrl_regs;
+ PnvPervasiveCtrlRegs control_regs;
+} PnvNestChipletPervasive;
+
+#endif /*PPC_PNV_NEST_PERVASIVE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index f5becbab41..3e15706dec 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_XIVE2_BASE 0x2010800
#define PNV10_XSCOM_XIVE2_SIZE 0x400
+#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
+#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
+
#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
diff --git a/hw/ppc/pnv_nest_pervasive.c b/hw/ppc/pnv_nest_pervasive.c
new file mode 100644
index 0000000000..0575f87e8f
--- /dev/null
+++ b/hw/ppc/pnv_nest_pervasive.c
@@ -0,0 +1,219 @@
+/*
+ * QEMU PowerPC nest pervasive common chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_nest_pervasive.h"
+
+/*
+ * Status, configuration, and control units in POWER chips is provided
+ * by the pervasive subsystem, which connects registers to the SCOM bus,
+ * which can be programmed by processor cores, other units on the chip,
+ * BMCs, or other POWER chips.
+ *
+ * A POWER10 chip is divided into logical pieces called chiplets. Chiplets
+ * are broadly divided into "core chiplets" (with the processor cores) and
+ * "nest chiplets" (with everything else). Each chiplet has an attachment
+ * to the nest_pervasiveasive bus (PIB) and with chiplet-specific registers.
+ * All nest chiplets have a common basic set of registers.
+ *
+ * This model will provide the registers fuctionality for common registers of
+ * nest unit (PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
+ *
+ * Currently this model provide the read/write fuctionality of chiplet control
+ * scom registers.
+ */
+
+#define CPLT_CONF0 0x08
+#define CPLT_CONF0_OR 0x18
+#define CPLT_CONF0_CLEAR 0x28
+#define CPLT_CONF1 0x09
+#define CPLT_CONF1_OR 0x19
+#define CPLT_CONF1_CLEAR 0x29
+#define CPLT_STAT0 0x100
+#define CPLT_MASK0 0x101
+#define CPLT_PROTECT_MODE 0x3FE
+#define CPLT_ATOMIC_CLOCK 0x3FF
+
+static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, unsigned size)
+{
+ PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
+ int reg = addr >> 3;
+ uint64_t val = ~0ull;
+
+ /* CPLT_CTRL0 to CPLT_CTRL5 */
+ for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
+ if (reg == i) {
+ return nest_pervasive->control_regs.cplt_ctrl[i];
+ } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+ "xscom read at 0x%" PRIx64 "\n",
+ __func__, (unsigned long)reg);
+ return val;
+ }
+ }
+
+ switch (reg) {
+ case CPLT_CONF0:
+ val = nest_pervasive->control_regs.cplt_cfg0;
+ break;
+ case CPLT_CONF0_OR:
+ case CPLT_CONF0_CLEAR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+ "xscom read at 0x%" PRIx64 "\n",
+ __func__, (unsigned long)reg);
+ break;
+ case CPLT_CONF1:
+ val = nest_pervasive->control_regs.cplt_cfg1;
+ break;
+ case CPLT_CONF1_OR:
+ case CPLT_CONF1_CLEAR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
+ "xscom read at 0x%" PRIx64 "\n",
+ __func__, (unsigned long)reg);
+ break;
+ case CPLT_STAT0:
+ val = nest_pervasive->control_regs.cplt_stat0;
+ break;
+ case CPLT_MASK0:
+ val = nest_pervasive->control_regs.cplt_mask0;
+ break;
+ case CPLT_PROTECT_MODE:
+ val = nest_pervasive->control_regs.ctrl_protect_mode;
+ break;
+ case CPLT_ATOMIC_CLOCK:
+ val = nest_pervasive->control_regs.ctrl_atomic_lock;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
+ "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg);
+ }
+ return val;
+}
+
+static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
+ int reg = addr >> 3;
+
+ /* CPLT_CTRL0 to CPLT_CTRL5 */
+ for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
+ if (reg == i) {
+ nest_pervasive->control_regs.cplt_ctrl[i] = val;
+ return;
+ } else if (reg == (i + 0x10)) {
+ nest_pervasive->control_regs.cplt_ctrl[i] |= val;
+ return;
+ } else if (reg == (i + 0x20)) {
+ nest_pervasive->control_regs.cplt_ctrl[i] &= ~val;
+ return;
+ }
+ }
+
+ switch (reg) {
+ case CPLT_CONF0:
+ nest_pervasive->control_regs.cplt_cfg0 = val;
+ break;
+ case CPLT_CONF0_OR:
+ nest_pervasive->control_regs.cplt_cfg0 |= val;
+ break;
+ case CPLT_CONF0_CLEAR:
+ nest_pervasive->control_regs.cplt_cfg0 &= ~val;
+ break;
+ case CPLT_CONF1:
+ nest_pervasive->control_regs.cplt_cfg1 = val;
+ break;
+ case CPLT_CONF1_OR:
+ nest_pervasive->control_regs.cplt_cfg1 |= val;
+ break;
+ case CPLT_CONF1_CLEAR:
+ nest_pervasive->control_regs.cplt_cfg1 &= ~val;
+ break;
+ case CPLT_STAT0:
+ nest_pervasive->control_regs.cplt_stat0 = val;
+ break;
+ case CPLT_MASK0:
+ nest_pervasive->control_regs.cplt_mask0 = val;
+ break;
+ case CPLT_PROTECT_MODE:
+ nest_pervasive->control_regs.ctrl_protect_mode = val;
+ break;
+ case CPLT_ATOMIC_CLOCK:
+ nest_pervasive->control_regs.ctrl_atomic_lock = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
+ "write at 0x%" PRIx64 "\n",
+ __func__, (unsigned long)reg);
+ }
+}
+
+static const MemoryRegionOps pnv_nest_pervasive_control_xscom_ops = {
+ .read = pnv_chiplet_ctrl_read,
+ .write = pnv_chiplet_ctrl_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp)
+{
+ PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(dev);
+ g_autofree char *region_name = NULL;
+ region_name = g_strdup_printf("xscom-%s-control-regs",
+ nest_pervasive->parent_obj_name);
+
+ /* Chiplet control scoms */
+ pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs,
+ OBJECT(nest_pervasive),
+ &pnv_nest_pervasive_control_xscom_ops,
+ nest_pervasive, region_name,
+ PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE);
+}
+
+static Property pnv_nest_pervasive_properties[] = {
+ DEFINE_PROP_STRING("parent-obj-name", PnvNestChipletPervasive,
+ parent_obj_name),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_nest_pervasive_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV nest_pervasive chiplet";
+ dc->realize = pnv_nest_pervasive_realize;
+ device_class_set_props(dc, pnv_nest_pervasive_properties);
+}
+
+static const TypeInfo pnv_nest_pervasive_info = {
+ .name = TYPE_PNV_NEST_PERVASIVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvNestChipletPervasive),
+ .class_init = pnv_nest_pervasive_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_nest_pervasive_register_types(void)
+{
+ type_register_static(&pnv_nest_pervasive_info);
+}
+
+type_init(pnv_nest_pervasive_register_types);
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index ea44856d43..d6f6f94fcc 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_bmc.c',
'pnv_homer.c',
'pnv_pnor.c',
+ 'pnv_nest_pervasive.c',
))
# PowerPC 4xx boards
ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common chiplet model
2023-11-27 17:13 ` [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common " Chalapathi V
@ 2023-11-28 2:04 ` Nicholas Piggin
2023-11-28 14:24 ` Cédric Le Goater
1 sibling, 0 replies; 12+ messages in thread
From: Nicholas Piggin @ 2023-11-28 2:04 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, clg, calebs, chalapathi.v, saif.abrar
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> are broadly divided into "core chiplets" (with the processor cores) and
> "nest chiplets" (with everything else). Each chiplet has an attachment
> to the pervasive bus (PIB) and with chiplet-specific registers. All nest
> chiplets have a common basic set of registers and This model will provide
> the registers functionality for common registers of nest chiplet (Pervasive
> Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
>
> This commit implement the read/write functions of chiplet control registers.
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_nest_pervasive.h | 36 +++++
> include/hw/ppc/pnv_xscom.h | 3 +
> hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++
> hw/ppc/meson.build | 1 +
> 4 files changed, 259 insertions(+)
> create mode 100644 include/hw/ppc/pnv_nest_pervasive.h
> create mode 100644 hw/ppc/pnv_nest_pervasive.c
>
> diff --git a/include/hw/ppc/pnv_nest_pervasive.h b/include/hw/ppc/pnv_nest_pervasive.h
> new file mode 100644
> index 0000000000..9f11531f52
> --- /dev/null
> +++ b/include/hw/ppc/pnv_nest_pervasive.h
> @@ -0,0 +1,36 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
Shouldn't need this line with the SPDX tag I think? There are a copule
of dozen files already in the tree that do have both, but hundreds that
only have the tag.
> + */
> +
> +#ifndef PPC_PNV_NEST_PERVASIVE_H
> +#define PPC_PNV_NEST_PERVASIVE_H
> +
> +#define TYPE_PNV_NEST_PERVASIVE "pnv-nest-chiplet-pervasive"
> +#define PNV_NEST_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_PERVASIVE)
_NEXT_CHIPLET_PERVASIVE?
> +
> +typedef struct PnvPervasiveCtrlRegs {
> +#define CPLT_CTRL_SIZE 6
> + uint64_t cplt_ctrl[CPLT_CTRL_SIZE];
> + uint64_t cplt_cfg0;
> + uint64_t cplt_cfg1;
> + uint64_t cplt_stat0;
> + uint64_t cplt_mask0;
> + uint64_t ctrl_protect_mode;
> + uint64_t ctrl_atomic_lock;
> +} PnvPervasiveCtrlRegs;
> +
> +typedef struct PnvNestChipletPervasive {
> + DeviceState parent;
> + char *parent_obj_name;
> + MemoryRegion xscom_ctrl_regs;
> + PnvPervasiveCtrlRegs control_regs;
> +} PnvNestChipletPervasive;
The file name doesn't quite match the type name, but that's probably
okay. This could be a good place for other misc pervasive helpers,
so keeping the name more general is fine.
> +
> +#endif /*PPC_PNV_NEST_PERVASIVE_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index f5becbab41..3e15706dec 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass {
> #define PNV10_XSCOM_XIVE2_BASE 0x2010800
> #define PNV10_XSCOM_XIVE2_SIZE 0x400
>
> +#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
> +#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
> +
> #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
> #define PNV10_XSCOM_PEC_NEST_SIZE 0x100
>
> diff --git a/hw/ppc/pnv_nest_pervasive.c b/hw/ppc/pnv_nest_pervasive.c
> new file mode 100644
> index 0000000000..0575f87e8f
> --- /dev/null
> +++ b/hw/ppc/pnv_nest_pervasive.c
> @@ -0,0 +1,219 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_xscom.h"
> +#include "hw/ppc/pnv_nest_pervasive.h"
> +
> +/*
> + * Status, configuration, and control units in POWER chips is provided
> + * by the pervasive subsystem, which connects registers to the SCOM bus,
> + * which can be programmed by processor cores, other units on the chip,
> + * BMCs, or other POWER chips.
> + *
> + * A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> + * are broadly divided into "core chiplets" (with the processor cores) and
> + * "nest chiplets" (with everything else). Each chiplet has an attachment
> + * to the nest_pervasiveasive bus (PIB) and with chiplet-specific registers.
> + * All nest chiplets have a common basic set of registers.
> + *
> + * This model will provide the registers fuctionality for common registers of
> + * nest unit (PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
> + *
> + * Currently this model provide the read/write fuctionality of chiplet control
> + * scom registers.
> + */
> +
> +#define CPLT_CONF0 0x08
> +#define CPLT_CONF0_OR 0x18
> +#define CPLT_CONF0_CLEAR 0x28
> +#define CPLT_CONF1 0x09
> +#define CPLT_CONF1_OR 0x19
> +#define CPLT_CONF1_CLEAR 0x29
> +#define CPLT_STAT0 0x100
> +#define CPLT_MASK0 0x101
> +#define CPLT_PROTECT_MODE 0x3FE
> +#define CPLT_ATOMIC_CLOCK 0x3FF
> +
> +static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> + uint64_t val = ~0ull;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + return nest_pervasive->control_regs.cplt_ctrl[i];
> + } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + return val;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + val = nest_pervasive->control_regs.cplt_cfg0;
> + break;
> + case CPLT_CONF0_OR:
> + case CPLT_CONF0_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_CONF1:
> + val = nest_pervasive->control_regs.cplt_cfg1;
> + break;
> + case CPLT_CONF1_OR:
> + case CPLT_CONF1_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_STAT0:
> + val = nest_pervasive->control_regs.cplt_stat0;
> + break;
> + case CPLT_MASK0:
> + val = nest_pervasive->control_regs.cplt_mask0;
> + break;
> + case CPLT_PROTECT_MODE:
> + val = nest_pervasive->control_regs.ctrl_protect_mode;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + val = nest_pervasive->control_regs.ctrl_atomic_lock;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg);
> + }
> + return val;
> +}
> +
> +static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + nest_pervasive->control_regs.cplt_ctrl[i] = val;
> + return;
> + } else if (reg == (i + 0x10)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] |= val;
> + return;
> + } else if (reg == (i + 0x20)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] &= ~val;
> + return;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + nest_pervasive->control_regs.cplt_cfg0 = val;
> + break;
> + case CPLT_CONF0_OR:
> + nest_pervasive->control_regs.cplt_cfg0 |= val;
> + break;
> + case CPLT_CONF0_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg0 &= ~val;
> + break;
> + case CPLT_CONF1:
> + nest_pervasive->control_regs.cplt_cfg1 = val;
> + break;
> + case CPLT_CONF1_OR:
> + nest_pervasive->control_regs.cplt_cfg1 |= val;
> + break;
> + case CPLT_CONF1_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg1 &= ~val;
> + break;
> + case CPLT_STAT0:
> + nest_pervasive->control_regs.cplt_stat0 = val;
> + break;
> + case CPLT_MASK0:
> + nest_pervasive->control_regs.cplt_mask0 = val;
> + break;
> + case CPLT_PROTECT_MODE:
> + nest_pervasive->control_regs.ctrl_protect_mode = val;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + nest_pervasive->control_regs.ctrl_atomic_lock = val;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "write at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_nest_pervasive_control_xscom_ops = {
> + .read = pnv_chiplet_ctrl_read,
> + .write = pnv_chiplet_ctrl_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(dev);
> + g_autofree char *region_name = NULL;
> + region_name = g_strdup_printf("xscom-%s-control-regs",
> + nest_pervasive->parent_obj_name);
Should it be just control, or pervasive-control? Nest chiplets will
have control for other functions.
Those are all minor nits though. Generally looks good.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> +
> + /* Chiplet control scoms */
> + pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs,
> + OBJECT(nest_pervasive),
> + &pnv_nest_pervasive_control_xscom_ops,
> + nest_pervasive, region_name,
> + PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE);
> +}
> +
> +static Property pnv_nest_pervasive_properties[] = {
> + DEFINE_PROP_STRING("parent-obj-name", PnvNestChipletPervasive,
> + parent_obj_name),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pnv_nest_pervasive_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV nest_pervasive chiplet";
> + dc->realize = pnv_nest_pervasive_realize;
> + device_class_set_props(dc, pnv_nest_pervasive_properties);
> +}
> +
> +static const TypeInfo pnv_nest_pervasive_info = {
> + .name = TYPE_PNV_NEST_PERVASIVE,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvNestChipletPervasive),
> + .class_init = pnv_nest_pervasive_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_PNV_XSCOM_INTERFACE },
> + { }
> + }
> +};
> +
> +static void pnv_nest_pervasive_register_types(void)
> +{
> + type_register_static(&pnv_nest_pervasive_info);
> +}
> +
> +type_init(pnv_nest_pervasive_register_types);
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index ea44856d43..d6f6f94fcc 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_bmc.c',
> 'pnv_homer.c',
> 'pnv_pnor.c',
> + 'pnv_nest_pervasive.c',
> ))
> # PowerPC 4xx boards
> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common chiplet model
2023-11-27 17:13 ` [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common " Chalapathi V
2023-11-28 2:04 ` Nicholas Piggin
@ 2023-11-28 14:24 ` Cédric Le Goater
1 sibling, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2023-11-28 14:24 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, calebs, chalapathi.v, saif.abrar
On 11/27/23 18:13, Chalapathi V wrote:
> A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> are broadly divided into "core chiplets" (with the processor cores) and
> "nest chiplets" (with everything else). Each chiplet has an attachment
> to the pervasive bus (PIB) and with chiplet-specific registers. All nest
> chiplets have a common basic set of registers and This model will provide
> the registers functionality for common registers of nest chiplet (Pervasive
> Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
>
> This commit implement the read/write functions of chiplet control registers.
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_nest_pervasive.h | 36 +++++
> include/hw/ppc/pnv_xscom.h | 3 +
> hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++
> hw/ppc/meson.build | 1 +
> 4 files changed, 259 insertions(+)
> create mode 100644 include/hw/ppc/pnv_nest_pervasive.h
> create mode 100644 hw/ppc/pnv_nest_pervasive.c
>
> diff --git a/include/hw/ppc/pnv_nest_pervasive.h b/include/hw/ppc/pnv_nest_pervasive.h
> new file mode 100644
> index 0000000000..9f11531f52
> --- /dev/null
> +++ b/include/hw/ppc/pnv_nest_pervasive.h
> @@ -0,0 +1,36 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#ifndef PPC_PNV_NEST_PERVASIVE_H
> +#define PPC_PNV_NEST_PERVASIVE_H
> +
> +#define TYPE_PNV_NEST_PERVASIVE "pnv-nest-chiplet-pervasive"
> +#define PNV_NEST_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_PERVASIVE)
> +
> +typedef struct PnvPervasiveCtrlRegs {
> +#define CPLT_CTRL_SIZE 6
> + uint64_t cplt_ctrl[CPLT_CTRL_SIZE];
> + uint64_t cplt_cfg0;
> + uint64_t cplt_cfg1;
> + uint64_t cplt_stat0;
> + uint64_t cplt_mask0;
> + uint64_t ctrl_protect_mode;
> + uint64_t ctrl_atomic_lock;
> +} PnvPervasiveCtrlRegs;
> +
> +typedef struct PnvNestChipletPervasive {
> + DeviceState parent;
> + char *parent_obj_name;
> + MemoryRegion xscom_ctrl_regs;
> + PnvPervasiveCtrlRegs control_regs;
> +} PnvNestChipletPervasive;
> +
> +#endif /*PPC_PNV_NEST_PERVASIVE_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index f5becbab41..3e15706dec 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass {
> #define PNV10_XSCOM_XIVE2_BASE 0x2010800
> #define PNV10_XSCOM_XIVE2_SIZE 0x400
>
> +#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
> +#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
> +
> #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
> #define PNV10_XSCOM_PEC_NEST_SIZE 0x100
>
> diff --git a/hw/ppc/pnv_nest_pervasive.c b/hw/ppc/pnv_nest_pervasive.c
> new file mode 100644
> index 0000000000..0575f87e8f
> --- /dev/null
> +++ b/hw/ppc/pnv_nest_pervasive.c
> @@ -0,0 +1,219 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_xscom.h"
> +#include "hw/ppc/pnv_nest_pervasive.h"
> +
> +/*
> + * Status, configuration, and control units in POWER chips is provided
> + * by the pervasive subsystem, which connects registers to the SCOM bus,
> + * which can be programmed by processor cores, other units on the chip,
> + * BMCs, or other POWER chips.
> + *
> + * A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> + * are broadly divided into "core chiplets" (with the processor cores) and
> + * "nest chiplets" (with everything else). Each chiplet has an attachment
> + * to the nest_pervasiveasive bus (PIB) and with chiplet-specific registers.
> + * All nest chiplets have a common basic set of registers.
> + *
> + * This model will provide the registers fuctionality for common registers of
> + * nest unit (PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
> + *
> + * Currently this model provide the read/write fuctionality of chiplet control
> + * scom registers.
> + */
> +
> +#define CPLT_CONF0 0x08
> +#define CPLT_CONF0_OR 0x18
> +#define CPLT_CONF0_CLEAR 0x28
> +#define CPLT_CONF1 0x09
> +#define CPLT_CONF1_OR 0x19
> +#define CPLT_CONF1_CLEAR 0x29
> +#define CPLT_STAT0 0x100
> +#define CPLT_MASK0 0x101
> +#define CPLT_PROTECT_MODE 0x3FE
> +#define CPLT_ATOMIC_CLOCK 0x3FF
> +
> +static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> + uint64_t val = ~0ull;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + return nest_pervasive->control_regs.cplt_ctrl[i];
> + } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
Please remove this cast and the ones below, it will break compile on
some platform. PRIx32 should be fine. reg should be unsigned AFAICT.
Thanks,
C.
> + return val;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + val = nest_pervasive->control_regs.cplt_cfg0;
> + break;
> + case CPLT_CONF0_OR:
> + case CPLT_CONF0_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_CONF1:
> + val = nest_pervasive->control_regs.cplt_cfg1;
> + break;
> + case CPLT_CONF1_OR:
> + case CPLT_CONF1_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_STAT0:
> + val = nest_pervasive->control_regs.cplt_stat0;
> + break;
> + case CPLT_MASK0:
> + val = nest_pervasive->control_regs.cplt_mask0;
> + break;
> + case CPLT_PROTECT_MODE:
> + val = nest_pervasive->control_regs.ctrl_protect_mode;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + val = nest_pervasive->control_regs.ctrl_atomic_lock;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg);
> + }
> + return val;
> +}
> +
> +static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + nest_pervasive->control_regs.cplt_ctrl[i] = val;
> + return;
> + } else if (reg == (i + 0x10)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] |= val;
> + return;
> + } else if (reg == (i + 0x20)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] &= ~val;
> + return;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + nest_pervasive->control_regs.cplt_cfg0 = val;
> + break;
> + case CPLT_CONF0_OR:
> + nest_pervasive->control_regs.cplt_cfg0 |= val;
> + break;
> + case CPLT_CONF0_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg0 &= ~val;
> + break;
> + case CPLT_CONF1:
> + nest_pervasive->control_regs.cplt_cfg1 = val;
> + break;
> + case CPLT_CONF1_OR:
> + nest_pervasive->control_regs.cplt_cfg1 |= val;
> + break;
> + case CPLT_CONF1_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg1 &= ~val;
> + break;
> + case CPLT_STAT0:
> + nest_pervasive->control_regs.cplt_stat0 = val;
> + break;
> + case CPLT_MASK0:
> + nest_pervasive->control_regs.cplt_mask0 = val;
> + break;
> + case CPLT_PROTECT_MODE:
> + nest_pervasive->control_regs.ctrl_protect_mode = val;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + nest_pervasive->control_regs.ctrl_atomic_lock = val;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "write at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_nest_pervasive_control_xscom_ops = {
> + .read = pnv_chiplet_ctrl_read,
> + .write = pnv_chiplet_ctrl_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(dev);
> + g_autofree char *region_name = NULL;
> + region_name = g_strdup_printf("xscom-%s-control-regs",
> + nest_pervasive->parent_obj_name);
> +
> + /* Chiplet control scoms */
> + pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs,
> + OBJECT(nest_pervasive),
> + &pnv_nest_pervasive_control_xscom_ops,
> + nest_pervasive, region_name,
> + PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE);
> +}
> +
> +static Property pnv_nest_pervasive_properties[] = {
> + DEFINE_PROP_STRING("parent-obj-name", PnvNestChipletPervasive,
> + parent_obj_name),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pnv_nest_pervasive_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV nest_pervasive chiplet";
> + dc->realize = pnv_nest_pervasive_realize;
> + device_class_set_props(dc, pnv_nest_pervasive_properties);
> +}
> +
> +static const TypeInfo pnv_nest_pervasive_info = {
> + .name = TYPE_PNV_NEST_PERVASIVE,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvNestChipletPervasive),
> + .class_init = pnv_nest_pervasive_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_PNV_XSCOM_INTERFACE },
> + { }
> + }
> +};
> +
> +static void pnv_nest_pervasive_register_types(void)
> +{
> + type_register_static(&pnv_nest_pervasive_info);
> +}
> +
> +type_init(pnv_nest_pervasive_register_types);
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index ea44856d43..d6f6f94fcc 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_bmc.c',
> 'pnv_homer.c',
> 'pnv_pnor.c',
> + 'pnv_nest_pervasive.c',
> ))
> # PowerPC 4xx boards
> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 2/3] hw/ppc: Add N1 chiplet model
2023-11-27 17:13 [PATCH v6 0/3] pnv nest1 chiplet model Chalapathi V
2023-11-27 17:13 ` [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common " Chalapathi V
@ 2023-11-27 17:13 ` Chalapathi V
2023-11-28 2:05 ` Nicholas Piggin
2023-11-28 6:48 ` Cédric Le Goater
2023-11-27 17:13 ` [PATCH v6 3/3] hw/ppc: N1 chiplet wiring Chalapathi V
2023-11-28 17:38 ` [PATCH v6 0/3] pnv nest1 chiplet model Cédric Le Goater
3 siblings, 2 replies; 12+ messages in thread
From: Chalapathi V @ 2023-11-27 17:13 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, clg, calebs, chalapathi.v,
chalapathi.v, saif.abrar
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
---
include/hw/ppc/pnv_n1_chiplet.h | 35 +++++++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++++++++++++
hw/ppc/meson.build | 1 +
4 files changed, 213 insertions(+)
create mode 100644 include/hw/ppc/pnv_n1_chiplet.h
create mode 100644 hw/ppc/pnv_n1_chiplet.c
diff --git a/include/hw/ppc/pnv_n1_chiplet.h b/include/hw/ppc/pnv_n1_chiplet.h
new file mode 100644
index 0000000000..3c42ada7f4
--- /dev/null
+++ b/include/hw/ppc/pnv_n1_chiplet.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU PowerPC N1 chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef PPC_PNV_N1_CHIPLET_H
+#define PPC_PNV_N1_CHIPLET_H
+
+#include "hw/ppc/pnv_nest_pervasive.h"
+
+#define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet"
+#define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj), TYPE_PNV_N1_CHIPLET)
+
+typedef struct pb_scom {
+ uint64_t mode;
+ uint64_t hp_mode2_curr;
+} pb_scom;
+
+typedef struct PnvN1Chiplet {
+ DeviceState parent;
+ MemoryRegion xscom_pb_eq_regs;
+ MemoryRegion xscom_pb_es_regs;
+ /* common pervasive chiplet unit */
+ PnvNestChipletPervasive nest_pervasive;
+ pb_scom eq[8];
+ pb_scom es[4];
+} PnvN1Chiplet;
+#endif /*PPC_PNV_N1_CHIPLET_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 3e15706dec..535ae1dab0 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -173,6 +173,12 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
+#define PNV10_XSCOM_N1_PB_SCOM_EQ_BASE 0x3011000
+#define PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE 0x200
+
+#define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300
+#define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100
+
#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
diff --git a/hw/ppc/pnv_n1_chiplet.c b/hw/ppc/pnv_n1_chiplet.c
new file mode 100644
index 0000000000..8e4c21dbf6
--- /dev/null
+++ b/hw/ppc/pnv_n1_chiplet.c
@@ -0,0 +1,171 @@
+/*
+ * QEMU PowerPC N1 chiplet model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/pnv_n1_chiplet.h"
+#include "hw/ppc/pnv_nest_pervasive.h"
+
+/*
+ * The n1 chiplet contains chiplet control unit,
+ * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU)
+ * and more.
+ *
+ * In this model Nest1 chiplet control registers are modelled via common
+ * nest pervasive model and few PowerBus racetrack registers are modelled.
+ */
+
+#define PB_SCOM_EQ0_HP_MODE2_CURR 0xe
+#define PB_SCOM_ES3_MODE 0x8a
+
+static uint64_t pnv_n1_chiplet_pb_scom_eq_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
+ int reg = addr >> 3;
+ uint64_t val = ~0ull;
+
+ switch (reg) {
+ case PB_SCOM_EQ0_HP_MODE2_CURR:
+ val = n1_chiplet->eq[0].hp_mode2_curr;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n",
+ __func__, reg);
+ }
+ return val;
+}
+
+static void pnv_n1_chiplet_pb_scom_eq_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
+ int reg = addr >> 3;
+
+ switch (reg) {
+ case PB_SCOM_EQ0_HP_MODE2_CURR:
+ n1_chiplet->eq[0].hp_mode2_curr = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n",
+ __func__, reg);
+ }
+}
+
+static const MemoryRegionOps pnv_n1_chiplet_pb_scom_eq_ops = {
+ .read = pnv_n1_chiplet_pb_scom_eq_read,
+ .write = pnv_n1_chiplet_pb_scom_eq_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static uint64_t pnv_n1_chiplet_pb_scom_es_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
+ int reg = addr >> 3;
+ uint64_t val = ~0ull;
+
+ switch (reg) {
+ case PB_SCOM_ES3_MODE:
+ val = n1_chiplet->es[3].mode;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n",
+ __func__, reg);
+ }
+ return val;
+}
+
+static void pnv_n1_chiplet_pb_scom_es_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
+ int reg = addr >> 3;
+
+ switch (reg) {
+ case PB_SCOM_ES3_MODE:
+ n1_chiplet->es[3].mode = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n",
+ __func__, reg);
+ }
+}
+
+static const MemoryRegionOps pnv_n1_chiplet_pb_scom_es_ops = {
+ .read = pnv_n1_chiplet_pb_scom_es_read,
+ .write = pnv_n1_chiplet_pb_scom_es_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_n1_chiplet_realize(DeviceState *dev, Error **errp)
+{
+ PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(dev);
+
+ /* Initialize and realize nest pervasive common chiplet model */
+ object_initialize_child(OBJECT(n1_chiplet), "nest_pervasive_common",
+ &n1_chiplet->nest_pervasive,
+ TYPE_PNV_NEST_PERVASIVE);
+ object_property_set_str(OBJECT(&n1_chiplet->nest_pervasive),
+ "parent-obj-name", "n1_chiplet", errp);
+ if (!qdev_realize(DEVICE(&n1_chiplet->nest_pervasive), NULL, errp)) {
+ return;
+ }
+
+ /* Nest1 chiplet power bus EQ xscom region */
+ pnv_xscom_region_init(&n1_chiplet->xscom_pb_eq_regs, OBJECT(n1_chiplet),
+ &pnv_n1_chiplet_pb_scom_eq_ops, n1_chiplet,
+ "xscom-n1_chiplet-pb-scom-eq-regs",
+ PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE);
+
+ /* Nest1 chiplet power bus ES xscom region */
+ pnv_xscom_region_init(&n1_chiplet->xscom_pb_es_regs, OBJECT(n1_chiplet),
+ &pnv_n1_chiplet_pb_scom_es_ops, n1_chiplet,
+ "xscom-n1_chiplet-pb-scom-es-regs",
+ PNV10_XSCOM_N1_PB_SCOM_ES_SIZE);
+}
+
+static void pnv_n1_chiplet_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV n1 chiplet";
+ dc->realize = pnv_n1_chiplet_realize;
+}
+
+static const TypeInfo pnv_n1_chiplet_info = {
+ .name = TYPE_PNV_N1_CHIPLET,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvN1Chiplet),
+ .class_init = pnv_n1_chiplet_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_n1_chiplet_register_types(void)
+{
+ type_register_static(&pnv_n1_chiplet_info);
+}
+
+type_init(pnv_n1_chiplet_register_types);
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index d6f6f94fcc..256e453c0c 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -52,6 +52,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_homer.c',
'pnv_pnor.c',
'pnv_nest_pervasive.c',
+ 'pnv_n1_chiplet.c',
))
# PowerPC 4xx boards
ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v6 2/3] hw/ppc: Add N1 chiplet model
2023-11-27 17:13 ` [PATCH v6 2/3] hw/ppc: Add N1 " Chalapathi V
@ 2023-11-28 2:05 ` Nicholas Piggin
2023-11-28 6:48 ` Cédric Le Goater
1 sibling, 0 replies; 12+ messages in thread
From: Nicholas Piggin @ 2023-11-28 2:05 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, clg, calebs, chalapathi.v, saif.abrar
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> The N1 chiplet handle the high speed i/o traffic over PCIe and others.
> The N1 chiplet consists of PowerBus Fabric controller,
> nest Memory Management Unit, chiplet control unit and more.
>
> This commit creates a N1 chiplet model and initialize and realize the
> pervasive chiplet model where chiplet control registers are implemented.
>
> This commit also implement the read/write method for the powerbus scom
> registers
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_n1_chiplet.h | 35 +++++++
> include/hw/ppc/pnv_xscom.h | 6 ++
> hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++++++++++++
> hw/ppc/meson.build | 1 +
> 4 files changed, 213 insertions(+)
> create mode 100644 include/hw/ppc/pnv_n1_chiplet.h
> create mode 100644 hw/ppc/pnv_n1_chiplet.c
>
> diff --git a/include/hw/ppc/pnv_n1_chiplet.h b/include/hw/ppc/pnv_n1_chiplet.h
> new file mode 100644
> index 0000000000..3c42ada7f4
> --- /dev/null
> +++ b/include/hw/ppc/pnv_n1_chiplet.h
> @@ -0,0 +1,35 @@
> +/*
> + * QEMU PowerPC N1 chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
Same question about tag here in in the .c. Otherwise,
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Thanks,
Nick
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 2/3] hw/ppc: Add N1 chiplet model
2023-11-27 17:13 ` [PATCH v6 2/3] hw/ppc: Add N1 " Chalapathi V
2023-11-28 2:05 ` Nicholas Piggin
@ 2023-11-28 6:48 ` Cédric Le Goater
2023-12-06 10:01 ` Chalapathi V
1 sibling, 1 reply; 12+ messages in thread
From: Cédric Le Goater @ 2023-11-28 6:48 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, calebs, chalapathi.v, saif.abrar
On 11/27/23 18:13, Chalapathi V wrote:
> The N1 chiplet handle the high speed i/o traffic over PCIe and others.
> The N1 chiplet consists of PowerBus Fabric controller,
> nest Memory Management Unit, chiplet control unit and more.
>
> This commit creates a N1 chiplet model and initialize and realize the
> pervasive chiplet model where chiplet control registers are implemented.
>
> This commit also implement the read/write method for the powerbus scom
> registers
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_n1_chiplet.h | 35 +++++++
> include/hw/ppc/pnv_xscom.h | 6 ++
> hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++++++++++++
> hw/ppc/meson.build | 1 +
> 4 files changed, 213 insertions(+)
> create mode 100644 include/hw/ppc/pnv_n1_chiplet.h
> create mode 100644 hw/ppc/pnv_n1_chiplet.c
>
> diff --git a/include/hw/ppc/pnv_n1_chiplet.h b/include/hw/ppc/pnv_n1_chiplet.h
> new file mode 100644
> index 0000000000..3c42ada7f4
> --- /dev/null
> +++ b/include/hw/ppc/pnv_n1_chiplet.h
> @@ -0,0 +1,35 @@
> +/*
> + * QEMU PowerPC N1 chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef PPC_PNV_N1_CHIPLET_H
> +#define PPC_PNV_N1_CHIPLET_H
> +
> +#include "hw/ppc/pnv_nest_pervasive.h"
> +
> +#define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet"
> +#define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj), TYPE_PNV_N1_CHIPLET)
> +
> +typedef struct pb_scom {
> + uint64_t mode;
> + uint64_t hp_mode2_curr;
> +} pb_scom;
Please use CamelCase coding style.
> +
> +typedef struct PnvN1Chiplet {
> + DeviceState parent;
> + MemoryRegion xscom_pb_eq_regs;
> + MemoryRegion xscom_pb_es_regs;
the MemoryRegion are generally called _mr, _iomem.
> + /* common pervasive chiplet unit */
> + PnvNestChipletPervasive nest_pervasive;
> + pb_scom eq[8];
> + pb_scom es[4];
are these arrays the registers ?
> +} PnvN1Chiplet;
> +#endif /*PPC_PNV_N1_CHIPLET_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index 3e15706dec..535ae1dab0 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -173,6 +173,12 @@ struct PnvXScomInterfaceClass {
> #define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
> #define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
>
> +#define PNV10_XSCOM_N1_PB_SCOM_EQ_BASE 0x3011000
> +#define PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE 0x200
> +
> +#define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300
> +#define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100
> +
> #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
> #define PNV10_XSCOM_PEC_NEST_SIZE 0x100
>
> diff --git a/hw/ppc/pnv_n1_chiplet.c b/hw/ppc/pnv_n1_chiplet.c
> new file mode 100644
> index 0000000000..8e4c21dbf6
> --- /dev/null
> +++ b/hw/ppc/pnv_n1_chiplet.c
> @@ -0,0 +1,171 @@
> +/*
> + * QEMU PowerPC N1 chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_xscom.h"
> +#include "hw/ppc/pnv_n1_chiplet.h"
> +#include "hw/ppc/pnv_nest_pervasive.h"
> +
> +/*
> + * The n1 chiplet contains chiplet control unit,
> + * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU)
> + * and more.
> + *
> + * In this model Nest1 chiplet control registers are modelled via common
> + * nest pervasive model and few PowerBus racetrack registers are modelled.
> + */
> +
> +#define PB_SCOM_EQ0_HP_MODE2_CURR 0xe
> +#define PB_SCOM_ES3_MODE 0x8a
> +
> +static uint64_t pnv_n1_chiplet_pb_scom_eq_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
> + int reg = addr >> 3;
> + uint64_t val = ~0ull;
> +
> + switch (reg) {
> + case PB_SCOM_EQ0_HP_MODE2_CURR:
> + val = n1_chiplet->eq[0].hp_mode2_curr;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n",
> + __func__, reg);
> + }
> + return val;
> +}
> +
> +static void pnv_n1_chiplet_pb_scom_eq_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
> + int reg = addr >> 3;
> +
> + switch (reg) {
> + case PB_SCOM_EQ0_HP_MODE2_CURR:
> + n1_chiplet->eq[0].hp_mode2_curr = val;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n",
> + __func__, reg);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_n1_chiplet_pb_scom_eq_ops = {
> + .read = pnv_n1_chiplet_pb_scom_eq_read,
> + .write = pnv_n1_chiplet_pb_scom_eq_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static uint64_t pnv_n1_chiplet_pb_scom_es_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
> + int reg = addr >> 3;
> + uint64_t val = ~0ull;
> +
> + switch (reg) {
> + case PB_SCOM_ES3_MODE:
> + val = n1_chiplet->es[3].mode;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n",
> + __func__, reg);
> + }
> + return val;
> +}
> +
> +static void pnv_n1_chiplet_pb_scom_es_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
> + int reg = addr >> 3;
> +
> + switch (reg) {
> + case PB_SCOM_ES3_MODE:
> + n1_chiplet->es[3].mode = val;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n",
> + __func__, reg);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_n1_chiplet_pb_scom_es_ops = {
> + .read = pnv_n1_chiplet_pb_scom_es_read,
> + .write = pnv_n1_chiplet_pb_scom_es_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void pnv_n1_chiplet_realize(DeviceState *dev, Error **errp)
> +{
> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(dev);
> +
> + /* Initialize and realize nest pervasive common chiplet model */
> + object_initialize_child(OBJECT(n1_chiplet), "nest_pervasive_common",
> + &n1_chiplet->nest_pervasive,
> + TYPE_PNV_NEST_PERVASIVE);
object_initialize_child() should be called from an instance_init handler.
> + object_property_set_str(OBJECT(&n1_chiplet->nest_pervasive),
> + "parent-obj-name", "n1_chiplet", errp);
is it that important to name the xscom region ?
Thanks,
C.
> + if (!qdev_realize(DEVICE(&n1_chiplet->nest_pervasive), NULL, errp)) {
> + return;
> + }
> +
> + /* Nest1 chiplet power bus EQ xscom region */
> + pnv_xscom_region_init(&n1_chiplet->xscom_pb_eq_regs, OBJECT(n1_chiplet),
> + &pnv_n1_chiplet_pb_scom_eq_ops, n1_chiplet,
> + "xscom-n1_chiplet-pb-scom-eq-regs",
> + PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE);
> +
> + /* Nest1 chiplet power bus ES xscom region */
> + pnv_xscom_region_init(&n1_chiplet->xscom_pb_es_regs, OBJECT(n1_chiplet),
> + &pnv_n1_chiplet_pb_scom_es_ops, n1_chiplet,
> + "xscom-n1_chiplet-pb-scom-es-regs",
> + PNV10_XSCOM_N1_PB_SCOM_ES_SIZE);
> +}
> +
> +static void pnv_n1_chiplet_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV n1 chiplet";
> + dc->realize = pnv_n1_chiplet_realize;
> +}
> +
> +static const TypeInfo pnv_n1_chiplet_info = {
> + .name = TYPE_PNV_N1_CHIPLET,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvN1Chiplet),
> + .class_init = pnv_n1_chiplet_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_PNV_XSCOM_INTERFACE },
> + { }
> + }
> +};
> +
> +static void pnv_n1_chiplet_register_types(void)
> +{
> + type_register_static(&pnv_n1_chiplet_info);
> +}
> +
> +type_init(pnv_n1_chiplet_register_types);
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index d6f6f94fcc..256e453c0c 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -52,6 +52,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_homer.c',
> 'pnv_pnor.c',
> 'pnv_nest_pervasive.c',
> + 'pnv_n1_chiplet.c',
> ))
> # PowerPC 4xx boards
> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v6 2/3] hw/ppc: Add N1 chiplet model
2023-11-28 6:48 ` Cédric Le Goater
@ 2023-12-06 10:01 ` Chalapathi V
0 siblings, 0 replies; 12+ messages in thread
From: Chalapathi V @ 2023-12-06 10:01 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, calebs, chalapathi.v, saif.abrar
On 28-11-2023 12:18, Cédric Le Goater wrote:
> On 11/27/23 18:13, Chalapathi V wrote:
>> The N1 chiplet handle the high speed i/o traffic over PCIe and others.
>> The N1 chiplet consists of PowerBus Fabric controller,
>> nest Memory Management Unit, chiplet control unit and more.
>>
>> This commit creates a N1 chiplet model and initialize and realize the
>> pervasive chiplet model where chiplet control registers are implemented.
>>
>> This commit also implement the read/write method for the powerbus scom
>> registers
>>
>> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
>> ---
>> include/hw/ppc/pnv_n1_chiplet.h | 35 +++++++
>> include/hw/ppc/pnv_xscom.h | 6 ++
>> hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++++++++++++
>> hw/ppc/meson.build | 1 +
>> 4 files changed, 213 insertions(+)
>> create mode 100644 include/hw/ppc/pnv_n1_chiplet.h
>> create mode 100644 hw/ppc/pnv_n1_chiplet.c
>>
>> diff --git a/include/hw/ppc/pnv_n1_chiplet.h
>> b/include/hw/ppc/pnv_n1_chiplet.h
>> new file mode 100644
>> index 0000000000..3c42ada7f4
>> --- /dev/null
>> +++ b/include/hw/ppc/pnv_n1_chiplet.h
>> @@ -0,0 +1,35 @@
>> +/*
>> + * QEMU PowerPC N1 chiplet model
>> + *
>> + * Copyright (c) 2023, IBM Corporation.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0-or-later
>> + *
>> + * This code is licensed under the GPL version 2 or later. See the
>> + * COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#ifndef PPC_PNV_N1_CHIPLET_H
>> +#define PPC_PNV_N1_CHIPLET_H
>> +
>> +#include "hw/ppc/pnv_nest_pervasive.h"
>> +
>> +#define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet"
>> +#define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj),
>> TYPE_PNV_N1_CHIPLET)
>> +
>> +typedef struct pb_scom {
>> + uint64_t mode;
>> + uint64_t hp_mode2_curr;
>> +} pb_scom;
>
> Please use CamelCase coding style.
>
Sure. Thank You
>
>> +
>> +typedef struct PnvN1Chiplet {
>> + DeviceState parent;
>> + MemoryRegion xscom_pb_eq_regs;
>> + MemoryRegion xscom_pb_es_regs;
>
> the MemoryRegion are generally called _mr, _iomem.
>
Sure. Updated in V7. Thank You.
>> + /* common pervasive chiplet unit */
>> + PnvNestChipletPervasive nest_pervasive;
>> + pb_scom eq[8];
>> + pb_scom es[4];
>
> are these arrays the registers ?
>
Yes, These are array of pb_scom EQ and ES registers. For now just
PB_SCOM_EQ0_HP_MODE2_CURR and PB_SCOM_ES3_MODE registers are modeled.
>> +} PnvN1Chiplet;
>> +#endif /*PPC_PNV_N1_CHIPLET_H */
>> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
>> index 3e15706dec..535ae1dab0 100644
>> --- a/include/hw/ppc/pnv_xscom.h
>> +++ b/include/hw/ppc/pnv_xscom.h
>> @@ -173,6 +173,12 @@ struct PnvXScomInterfaceClass {
>> #define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
>> #define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
>> +#define PNV10_XSCOM_N1_PB_SCOM_EQ_BASE 0x3011000
>> +#define PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE 0x200
>> +
>> +#define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300
>> +#define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100
>> +
>> #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes
>> downwards ... */
>> #define PNV10_XSCOM_PEC_NEST_SIZE 0x100
>> diff --git a/hw/ppc/pnv_n1_chiplet.c b/hw/ppc/pnv_n1_chiplet.c
>> new file mode 100644
>> index 0000000000..8e4c21dbf6
>> --- /dev/null
>> +++ b/hw/ppc/pnv_n1_chiplet.c
>> @@ -0,0 +1,171 @@
>> +/*
>> + * QEMU PowerPC N1 chiplet model
>> + *
>> + * Copyright (c) 2023, IBM Corporation.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0-or-later
>> + *
>> + * This code is licensed under the GPL version 2 or later. See the
>> + * COPYING file in the top-level directory.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/log.h"
>> +#include "hw/qdev-properties.h"
>> +#include "hw/ppc/pnv.h"
>> +#include "hw/ppc/pnv_xscom.h"
>> +#include "hw/ppc/pnv_n1_chiplet.h"
>> +#include "hw/ppc/pnv_nest_pervasive.h"
>> +
>> +/*
>> + * The n1 chiplet contains chiplet control unit,
>> + * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU)
>> + * and more.
>> + *
>> + * In this model Nest1 chiplet control registers are modelled via
>> common
>> + * nest pervasive model and few PowerBus racetrack registers are
>> modelled.
>> + */
>> +
>> +#define PB_SCOM_EQ0_HP_MODE2_CURR 0xe
>> +#define PB_SCOM_ES3_MODE 0x8a
>> +
>> +static uint64_t pnv_n1_chiplet_pb_scom_eq_read(void *opaque, hwaddr
>> addr,
>> + unsigned size)
>> +{
>> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
>> + int reg = addr >> 3;
>> + uint64_t val = ~0ull;
>> +
>> + switch (reg) {
>> + case PB_SCOM_EQ0_HP_MODE2_CURR:
>> + val = n1_chiplet->eq[0].hp_mode2_curr;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%"
>> PRIx32 "\n",
>> + __func__, reg);
>> + }
>> + return val;
>> +}
>> +
>> +static void pnv_n1_chiplet_pb_scom_eq_write(void *opaque, hwaddr addr,
>> + uint64_t val,
>> unsigned size)
>> +{
>> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
>> + int reg = addr >> 3;
>> +
>> + switch (reg) {
>> + case PB_SCOM_EQ0_HP_MODE2_CURR:
>> + n1_chiplet->eq[0].hp_mode2_curr = val;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%"
>> PRIx32 "\n",
>> + __func__, reg);
>> + }
>> +}
>> +
>> +static const MemoryRegionOps pnv_n1_chiplet_pb_scom_eq_ops = {
>> + .read = pnv_n1_chiplet_pb_scom_eq_read,
>> + .write = pnv_n1_chiplet_pb_scom_eq_write,
>> + .valid.min_access_size = 8,
>> + .valid.max_access_size = 8,
>> + .impl.min_access_size = 8,
>> + .impl.max_access_size = 8,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> +};
>> +
>> +static uint64_t pnv_n1_chiplet_pb_scom_es_read(void *opaque, hwaddr
>> addr,
>> + unsigned size)
>> +{
>> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
>> + int reg = addr >> 3;
>> + uint64_t val = ~0ull;
>> +
>> + switch (reg) {
>> + case PB_SCOM_ES3_MODE:
>> + val = n1_chiplet->es[3].mode;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%"
>> PRIx32 "\n",
>> + __func__, reg);
>> + }
>> + return val;
>> +}
>> +
>> +static void pnv_n1_chiplet_pb_scom_es_write(void *opaque, hwaddr addr,
>> + uint64_t val,
>> unsigned size)
>> +{
>> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(opaque);
>> + int reg = addr >> 3;
>> +
>> + switch (reg) {
>> + case PB_SCOM_ES3_MODE:
>> + n1_chiplet->es[3].mode = val;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%"
>> PRIx32 "\n",
>> + __func__, reg);
>> + }
>> +}
>> +
>> +static const MemoryRegionOps pnv_n1_chiplet_pb_scom_es_ops = {
>> + .read = pnv_n1_chiplet_pb_scom_es_read,
>> + .write = pnv_n1_chiplet_pb_scom_es_write,
>> + .valid.min_access_size = 8,
>> + .valid.max_access_size = 8,
>> + .impl.min_access_size = 8,
>> + .impl.max_access_size = 8,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> +};
>> +
>> +static void pnv_n1_chiplet_realize(DeviceState *dev, Error **errp)
>> +{
>> + PnvN1Chiplet *n1_chiplet = PNV_N1_CHIPLET(dev);
>> +
>> + /* Initialize and realize nest pervasive common chiplet model */
>> + object_initialize_child(OBJECT(n1_chiplet),
>> "nest_pervasive_common",
>> + &n1_chiplet->nest_pervasive,
>> + TYPE_PNV_NEST_PERVASIVE);
>
> object_initialize_child() should be called from an instance_init handler.
>
>
>> + object_property_set_str(OBJECT(&n1_chiplet->nest_pervasive),
>> + "parent-obj-name", "n1_chiplet",
>> errp);
>
> is it that important to name the xscom region ?
>
No. not needed. I have removed this property in V7. Thank You.
>
> Thanks,
>
> C.
>
>
>
>> + if (!qdev_realize(DEVICE(&n1_chiplet->nest_pervasive), NULL,
>> errp)) {
>> + return;
>> + }
>> +
>> + /* Nest1 chiplet power bus EQ xscom region */
>> + pnv_xscom_region_init(&n1_chiplet->xscom_pb_eq_regs,
>> OBJECT(n1_chiplet),
>> + &pnv_n1_chiplet_pb_scom_eq_ops, n1_chiplet,
>> + "xscom-n1_chiplet-pb-scom-eq-regs",
>> + PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE);
>> +
>> + /* Nest1 chiplet power bus ES xscom region */
>> + pnv_xscom_region_init(&n1_chiplet->xscom_pb_es_regs,
>> OBJECT(n1_chiplet),
>> + &pnv_n1_chiplet_pb_scom_es_ops, n1_chiplet,
>> + "xscom-n1_chiplet-pb-scom-es-regs",
>> + PNV10_XSCOM_N1_PB_SCOM_ES_SIZE);
>> +}
>> +
>> +static void pnv_n1_chiplet_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->desc = "PowerNV n1 chiplet";
>> + dc->realize = pnv_n1_chiplet_realize;
>> +}
>> +
>> +static const TypeInfo pnv_n1_chiplet_info = {
>> + .name = TYPE_PNV_N1_CHIPLET,
>> + .parent = TYPE_DEVICE,
>> + .instance_size = sizeof(PnvN1Chiplet),
>> + .class_init = pnv_n1_chiplet_class_init,
>> + .interfaces = (InterfaceInfo[]) {
>> + { TYPE_PNV_XSCOM_INTERFACE },
>> + { }
>> + }
>> +};
>> +
>> +static void pnv_n1_chiplet_register_types(void)
>> +{
>> + type_register_static(&pnv_n1_chiplet_info);
>> +}
>> +
>> +type_init(pnv_n1_chiplet_register_types);
>> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
>> index d6f6f94fcc..256e453c0c 100644
>> --- a/hw/ppc/meson.build
>> +++ b/hw/ppc/meson.build
>> @@ -52,6 +52,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
>> 'pnv_homer.c',
>> 'pnv_pnor.c',
>> 'pnv_nest_pervasive.c',
>> + 'pnv_n1_chiplet.c',
>> ))
>> # PowerPC 4xx boards
>> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 3/3] hw/ppc: N1 chiplet wiring
2023-11-27 17:13 [PATCH v6 0/3] pnv nest1 chiplet model Chalapathi V
2023-11-27 17:13 ` [PATCH v6 1/3] hw/ppc: Add pnv nest pervasive common " Chalapathi V
2023-11-27 17:13 ` [PATCH v6 2/3] hw/ppc: Add N1 " Chalapathi V
@ 2023-11-27 17:13 ` Chalapathi V
2023-11-28 2:09 ` Nicholas Piggin
2023-11-28 17:38 ` [PATCH v6 0/3] pnv nest1 chiplet model Cédric Le Goater
3 siblings, 1 reply; 12+ messages in thread
From: Chalapathi V @ 2023-11-27 17:13 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, clg, calebs, chalapathi.v,
chalapathi.v, saif.abrar
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 0ab5c42308..9b06c8d87c 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -4,6 +4,7 @@
#include "hw/pci-host/pnv_phb4.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_n1_chiplet.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_psi.h"
@@ -113,6 +114,7 @@ struct Pnv10Chip {
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
+ PnvN1Chiplet n1_chiplet;
uint32_t nr_quads;
PnvQuad *quads;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0297871bdd..6cf1f3319f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1680,6 +1680,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
+ object_initialize_child(obj, "n1_chiplet", &chip10->n1_chiplet,
+ TYPE_PNV_N1_CHIPLET);
chip->num_pecs = pcc->num_pecs;
@@ -1849,6 +1851,19 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
&chip10->homer.regs);
+ /* N1 chiplet */
+ if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
+ &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
+ &chip10->n1_chiplet.xscom_pb_eq_regs);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
+ &chip10->n1_chiplet.xscom_pb_es_regs);
+
/* PHBs */
pnv_chip_power10_phb_realize(chip, &local_err);
if (local_err) {
--
2.31.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v6 3/3] hw/ppc: N1 chiplet wiring
2023-11-27 17:13 ` [PATCH v6 3/3] hw/ppc: N1 chiplet wiring Chalapathi V
@ 2023-11-28 2:09 ` Nicholas Piggin
0 siblings, 0 replies; 12+ messages in thread
From: Nicholas Piggin @ 2023-11-28 2:09 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, clg, calebs, chalapathi.v, saif.abrar
On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> This part of the patchset connects the nest1 chiplet model to p10 chip.
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_chip.h | 2 ++
> hw/ppc/pnv.c | 15 +++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index 0ab5c42308..9b06c8d87c 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -4,6 +4,7 @@
> #include "hw/pci-host/pnv_phb4.h"
> #include "hw/ppc/pnv_core.h"
> #include "hw/ppc/pnv_homer.h"
> +#include "hw/ppc/pnv_n1_chiplet.h"
> #include "hw/ppc/pnv_lpc.h"
> #include "hw/ppc/pnv_occ.h"
> #include "hw/ppc/pnv_psi.h"
> @@ -113,6 +114,7 @@ struct Pnv10Chip {
> PnvOCC occ;
> PnvSBE sbe;
> PnvHomer homer;
> + PnvN1Chiplet n1_chiplet;
>
> uint32_t nr_quads;
> PnvQuad *quads;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 0297871bdd..6cf1f3319f 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1680,6 +1680,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
> object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
> object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
> object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
> + object_initialize_child(obj, "n1_chiplet", &chip10->n1_chiplet,
> + TYPE_PNV_N1_CHIPLET);
Another very small nit, we seem to have convention of minus rather than
underscore for these names, so n1-chiplet fits better.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> chip->num_pecs = pcc->num_pecs;
>
> @@ -1849,6 +1851,19 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
> &chip10->homer.regs);
>
> + /* N1 chiplet */
> + if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) {
> + return;
> + }
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
> + &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs);
> +
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE,
> + &chip10->n1_chiplet.xscom_pb_eq_regs);
> +
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
> + &chip10->n1_chiplet.xscom_pb_es_regs);
> +
> /* PHBs */
> pnv_chip_power10_phb_realize(chip, &local_err);
> if (local_err) {
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 0/3] pnv nest1 chiplet model
2023-11-27 17:13 [PATCH v6 0/3] pnv nest1 chiplet model Chalapathi V
` (2 preceding siblings ...)
2023-11-27 17:13 ` [PATCH v6 3/3] hw/ppc: N1 chiplet wiring Chalapathi V
@ 2023-11-28 17:38 ` Cédric Le Goater
2023-11-28 21:37 ` Cédric Le Goater
3 siblings, 1 reply; 12+ messages in thread
From: Cédric Le Goater @ 2023-11-28 17:38 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, calebs, chalapathi.v, saif.abrar
On 11/27/23 18:13, Chalapathi V wrote:
> Hello,
>
> Thank you for the review and suggestions on V5.
>
> The suggestions and changes requested from V5 are addressed in V6.
>
> Updates in Version 6 of this series are:
> 1. adding a device-tree node in QEMU is removed as skiboot defines the
> device-tree and QEMU should just follow it.
> 2. Renamed PnvPerv to PnvNestChipletPervasive in PATCH1 as the model provides
> the common pervasive registers of all nest chiplets.
> 3. Nest1_chiplet model in PATCH2 is renamed to N1_chiplet to avoid the
> confussions that may comeup later.
>
> Hence the new qom-tree looks like below.
> (qemu) info qom-tree
> /machine (powernv10-machine)
> /chip[0] (power10_v2.0-pnv-chip)
> /n1_chiplet (pnv-N1-chiplet)
> /nest_pervasive_common (pnv-nest-chiplet-pervasive)
> /xscom-n1_chiplet-control-regs[0] (memory-region)
> /xscom-n1_chiplet-pb-scom-eq-regs[0] (memory-region)
> /xscom-n1_chiplet-pb-scom-es-regs[0] (memory-region)
>
> Patches overview in V6.
> PATCH1: Create a common nest pervasive chiplet model with control chiplet scom
> registers.
> PATCH2: Create a N1 chiplet model and implement powerbus scom registers.
> Connect common nest pervasive model to N1 chiplet model to define
> chiplet control scoms for N1 chiplet.
> PATCH3: Connect N1 chiplet model to p10 chip.
>
> Test covered:
> These changes are tested on a single socket and 2 socket P10 machine.
It would be nice to add in tests/avocado/ppc_powernv.py a simple test case
for a 2 socket machine :
self.vm.add_args('-smp', '8,sockets=2,cores=1,threads=4')
...
console_pattern = 'smp: Brought up 2 nodes, 8 CPUs'
Thanks,
C.
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v6 0/3] pnv nest1 chiplet model
2023-11-28 17:38 ` [PATCH v6 0/3] pnv nest1 chiplet model Cédric Le Goater
@ 2023-11-28 21:37 ` Cédric Le Goater
0 siblings, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2023-11-28 21:37 UTC (permalink / raw)
To: Chalapathi V, qemu-devel
Cc: qemu-ppc, fbarrat, npiggin, calebs, chalapathi.v, saif.abrar
On 11/28/23 18:38, Cédric Le Goater wrote:
> On 11/27/23 18:13, Chalapathi V wrote:
>> Hello,
>>
>> Thank you for the review and suggestions on V5.
>>
>> The suggestions and changes requested from V5 are addressed in V6.
>>
>> Updates in Version 6 of this series are:
>> 1. adding a device-tree node in QEMU is removed as skiboot defines the
>> device-tree and QEMU should just follow it.
>> 2. Renamed PnvPerv to PnvNestChipletPervasive in PATCH1 as the model provides
>> the common pervasive registers of all nest chiplets.
>> 3. Nest1_chiplet model in PATCH2 is renamed to N1_chiplet to avoid the
>> confussions that may comeup later.
>>
>> Hence the new qom-tree looks like below.
>> (qemu) info qom-tree
>> /machine (powernv10-machine)
>> /chip[0] (power10_v2.0-pnv-chip)
>> /n1_chiplet (pnv-N1-chiplet)
>> /nest_pervasive_common (pnv-nest-chiplet-pervasive)
>> /xscom-n1_chiplet-control-regs[0] (memory-region)
>> /xscom-n1_chiplet-pb-scom-eq-regs[0] (memory-region)
>> /xscom-n1_chiplet-pb-scom-es-regs[0] (memory-region)
>>
>> Patches overview in V6.
>> PATCH1: Create a common nest pervasive chiplet model with control chiplet scom
>> registers.
>> PATCH2: Create a N1 chiplet model and implement powerbus scom registers.
>> Connect common nest pervasive model to N1 chiplet model to define
>> chiplet control scoms for N1 chiplet.
>> PATCH3: Connect N1 chiplet model to p10 chip.
>>
>> Test covered:
>> These changes are tested on a single socket and 2 socket P10 machine.
>
>
> It would be nice to add in tests/avocado/ppc_powernv.py a simple test case
> for a 2 socket machine :
>
> self.vm.add_args('-smp', '8,sockets=2,cores=1,threads=4')
> ...
> console_pattern = 'smp: Brought up 2 nodes, 8 CPUs'
and test_linux_big_boot already exists ! :) Please run "make check
&& make check-avocado" before sending a patchset. This is a good way
to catch issues.
Thanks,
C.
^ permalink raw reply [flat|nested] 12+ messages in thread