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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c453328sm32453021f8f.46.2025.08.08.09.05.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 09:05:22 -0700 (PDT) Message-ID: Date: Fri, 8 Aug 2025 18:05:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 08/14] hw/misc: Add RISC-V CMGCR device implementation To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> <20250717093833.402237-9-djordje.todorovic@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250717093833.402237-9-djordje.todorovic@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 17/7/25 11:38, Djordje Todorovic wrote: > Add RISC-V implementation of the Coherent Manager Global Control > Register (CMGCR) device. It is based on the existing MIPS CMGCR > implementation but adapted for RISC-V systems. > > The CMGCR device provides global system control for multi-core > configurations in RISC-V systems. > > This is needed for the MIPS BOSTON AIA board. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Djordje Todorovic > --- > hw/misc/Kconfig | 10 ++ > hw/misc/meson.build | 2 + > hw/misc/riscv_cmgcr.c | 234 ++++++++++++++++++++++++++++++++++ > include/hw/misc/riscv_cmgcr.h | 49 +++++++ > 4 files changed, 295 insertions(+) > create mode 100644 hw/misc/riscv_cmgcr.c > create mode 100644 include/hw/misc/riscv_cmgcr.h > > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig > index ec0fa5aa9f..e3fce37c01 100644 > --- a/hw/misc/Kconfig > +++ b/hw/misc/Kconfig > @@ -108,6 +108,16 @@ config STM32L4X5_RCC > config MIPS_ITU > bool > > +config RISCV_CMGCR > + bool > + default n $ git grep 'default n' $(git ls-files|fgrep Kconfig) | wc -l 0 I remember asking that already but maybe it was a different series... Why don't you want this automatically selected by default? All our codebase does it, why change suddenly?