* [PATCH 1/3] target/loongarch: Add detailed information with CPU Product ID
2025-11-06 8:40 [PATCH 0/3] target/loongarch: Add host CPU type support Bibo Mao
@ 2025-11-06 8:40 ` Bibo Mao
2025-11-06 8:40 ` [PATCH 2/3] target/loongarch: Add generic CPU model information Bibo Mao
2025-11-06 8:40 ` [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode Bibo Mao
2 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-11-06 8:40 UTC (permalink / raw)
To: Song Gao; +Cc: Jiaxun Yang, qemu-devel
CPUCFG0 is LoongArch CPU Product ID, it is a combination of Vendor ID,
Series ID and Product ID, here is the layout:
+-------------+----------------+------------+----------------+
| Reserved | Vendor ID | Series ID | Product ID |
+-------------+----------------+------------+----------------+
31 24 23 16 15 12 11 0
Here adds detailed information with CPUCFG0, it is convenient to add
such information with host or LA664 CPU type in future.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu.c | 12 ++++++++++--
target/loongarch/cpu.h | 10 +++++++++-
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d74c3c3766..68ae3aff97 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -278,8 +278,12 @@ static void loongarch_la464_initfn(Object *obj)
}
cpu->dtb_compatible = "loongarch,Loongson-3A5000";
- env->cpucfg[0] = 0x14c010; /* PRID */
+ data = FIELD_DP32(data, CPUCFG0, PRID, 0x10);
+ data = FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA464);
+ data = FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON);
+ env->cpucfg[0] = data;
+ data = 0;
data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
@@ -385,8 +389,12 @@ static void loongarch_la132_initfn(Object *obj)
}
cpu->dtb_compatible = "loongarch,Loongson-1C103";
- env->cpucfg[0] = 0x148042; /* PRID */
+ data = FIELD_DP32(data, CPUCFG0, PRID, 0x42);
+ data = FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA132);
+ data = FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON);
+ env->cpucfg[0] = data;
+ data = 0;
data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 1a14469b3b..c00ad67457 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -97,7 +97,15 @@ FIELD(FCSR0, CAUSE, 24, 5)
#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
/* cpucfg[0] bits */
-FIELD(CPUCFG0, PRID, 0, 32)
+FIELD(CPUCFG0, PRID, 0, 12)
+FIELD(CPUCFG0, SERID, 12, 4)
+FIELD(CPUCFG0, VENID, 16, 8)
+#define PRID_SERIES_LA132 0x8 /* Loongson 32bit */
+#define PRID_SERIES_LA264 0xa /* Loongson 64bit, 2-issue */
+#define PRID_SERIES_LA364 0xb /* Loongson 64bit, 3-issue */
+#define PRID_SERIES_LA464 0xc /* Loongson 64bit, 4-issue */
+#define PRID_SERIES_LA664 0xd /* Loongson 64bit, 6-issue */
+#define PRID_VENDOR_LOONGSON 0x14
/* cpucfg[1] bits */
FIELD(CPUCFG1, ARCH, 0, 2)
base-commit: a8e63c013016f9ff981689189c5b063551d04559
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] target/loongarch: Add generic CPU model information
2025-11-06 8:40 [PATCH 0/3] target/loongarch: Add host CPU type support Bibo Mao
2025-11-06 8:40 ` [PATCH 1/3] target/loongarch: Add detailed information with CPU Product ID Bibo Mao
@ 2025-11-06 8:40 ` Bibo Mao
2025-11-06 8:40 ` [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode Bibo Mao
2 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-11-06 8:40 UTC (permalink / raw)
To: Song Gao; +Cc: Jiaxun Yang, qemu-devel
On LoongArch system, CPU model name comes from IOCSR register
LOONGARCH_IOCSR_VENDOR and LOONGARCH_IOCSR_CPUNAME. Its value
can be initialized when CPU is created.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
hw/loongarch/virt.c | 6 ++++--
target/loongarch/cpu.c | 4 ++++
target/loongarch/cpu.h | 6 ++++++
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 49434ad182..3ae723239f 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -635,7 +635,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(opaque);
uint64_t ret = 0;
int features;
+ CPULoongArchState *env;
+ env = &LOONGARCH_CPU(first_cpu)->env;
switch (addr) {
case VERSION_REG:
ret = 0x11ULL;
@@ -650,10 +652,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr,
}
break;
case VENDOR_REG:
- ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */
+ ret = env->vendor_id;
break;
case CPUNAME_REG:
- ret = 0x303030354133ULL; /* "3A5000" */
+ ret = env->cpu_id;
break;
case MISC_FUNC_REG:
if (kvm_irqchip_in_kernel()) {
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 68ae3aff97..8b8723a343 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -282,6 +282,8 @@ static void loongarch_la464_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA464);
data = FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON);
env->cpucfg[0] = data;
+ memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8);
+ memccpy((void *)&env->cpu_id, CPU_MODEL_3A5000, 0, 8);
data = 0;
data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
@@ -393,6 +395,8 @@ static void loongarch_la132_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA132);
data = FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON);
env->cpucfg[0] = data;
+ memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8);
+ memccpy((void *)&env->cpu_id, CPU_MODEL_1C101, 0, 8);
data = 0;
data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index c00ad67457..6cda47ee96 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -301,6 +301,10 @@ typedef struct LoongArchBT {
uint32_t ftop;
} lbt_t;
+#define CPU_VENDOR_LOONGSON "Loongson"
+#define CPU_MODEL_3A5000 "3A5000"
+#define CPU_MODEL_1C101 "1C101"
+
typedef struct CPUArchState {
uint64_t gpr[32];
uint64_t pc;
@@ -312,6 +316,8 @@ typedef struct CPUArchState {
uint32_t cpucfg[21];
uint32_t pv_features;
+ uint64_t vendor_id;
+ uint64_t cpu_id;
/* LoongArch CSRs */
uint64_t CSR_CRMD;
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode
2025-11-06 8:40 [PATCH 0/3] target/loongarch: Add host CPU type support Bibo Mao
2025-11-06 8:40 ` [PATCH 1/3] target/loongarch: Add detailed information with CPU Product ID Bibo Mao
2025-11-06 8:40 ` [PATCH 2/3] target/loongarch: Add generic CPU model information Bibo Mao
@ 2025-11-06 8:40 ` Bibo Mao
2025-12-04 1:57 ` lixianglai
2 siblings, 1 reply; 6+ messages in thread
From: Bibo Mao @ 2025-11-06 8:40 UTC (permalink / raw)
To: Song Gao; +Cc: Jiaxun Yang, qemu-devel
Host CPU model is basically the same with max CPU model, except Product
ID and CPU model name. With host CPU model, Product ID comes from
cpucfg0 and CPU model comes from /proc/cpuinfo.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu.c | 94 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 8b8723a343..c7f52adeb9 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -429,6 +429,97 @@ static void loongarch_max_initfn(Object *obj)
}
}
+#if defined(CONFIG_KVM)
+static int read_cpuinfo(const char *field, char *value, int len)
+{
+ FILE *f;
+ int ret = -1;
+ int field_len = strlen(field);
+ char line[512];
+
+ f = fopen("/proc/cpuinfo", "r");
+ if (!f) {
+ return -1;
+ }
+
+ do {
+ if (!fgets(line, sizeof(line), f)) {
+ break;
+ }
+ if (!strncmp(line, field, field_len)) {
+ strncpy(value, line, len);
+ ret = 0;
+ break;
+ }
+ } while (*line);
+
+ fclose(f);
+
+ return ret;
+}
+
+static uint64_t get_host_cpu_model(void)
+{
+ char line[512];
+ char *ns;
+ static uint64_t cpuid;
+
+ if (cpuid) {
+ return cpuid;
+ }
+
+ if (read_cpuinfo("Model Name", line, sizeof(line))) {
+ return 0;
+ }
+
+ ns = strchr(line, ':');
+ if (!ns) {
+ return 0;
+ }
+
+ ns = strstr(ns, "Loongson-");
+ if (!ns) {
+ return 0;
+ }
+
+ ns += strlen("Loongson-");
+ memccpy((void *)&cpuid, ns, 0, 8);
+ return cpuid;
+}
+
+static uint32_t get_host_cpucfg(int number)
+{
+ unsigned int data = 0;
+
+#ifdef __loongarch__
+ asm volatile("cpucfg %[val], %[reg]"
+ : [val] "=r" (data)
+ : [reg] "r" (number)
+ : "memory");
+#endif
+
+ return data;
+}
+
+static void loongarch_host_initfn(Object *obj)
+{
+ uint32_t data;
+ uint64_t cpuid;
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+
+ loongarch_max_initfn(obj);
+ data = get_host_cpucfg(0);
+ if (data) {
+ cpu->env.cpucfg[0] = data;
+ }
+
+ cpuid = get_host_cpu_model();
+ if (cpuid) {
+ cpu->env.cpu_id = cpuid;
+ }
+}
+#endif
+
static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
{
uint8_t tlb_ps;
@@ -780,6 +871,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
+#if defined(CONFIG_KVM)
+ DEFINE_LOONGARCH_CPU_TYPE(64, "host", loongarch_host_initfn),
+#endif
};
DEFINE_TYPES(loongarch_cpu_type_infos)
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode
2025-11-06 8:40 ` [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode Bibo Mao
@ 2025-12-04 1:57 ` lixianglai
2025-12-04 2:58 ` Bibo Mao
0 siblings, 1 reply; 6+ messages in thread
From: lixianglai @ 2025-12-04 1:57 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
Hi Bibo Mao:
> Host CPU model is basically the same with max CPU model, except Product
> ID and CPU model name. With host CPU model, Product ID comes from
> cpucfg0 and CPU model comes from /proc/cpuinfo.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/cpu.c | 94 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 8b8723a343..c7f52adeb9 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -429,6 +429,97 @@ static void loongarch_max_initfn(Object *obj)
> }
> }
>
> +#if defined(CONFIG_KVM)
> +static int read_cpuinfo(const char *field, char *value, int len)
> +{
> + FILE *f;
> + int ret = -1;
> + int field_len = strlen(field);
> + char line[512];
> +
> + f = fopen("/proc/cpuinfo", "r");
> + if (!f) {
> + return -1;
> + }
> +
> + do {
> + if (!fgets(line, sizeof(line), f)) {
> + break;
> + }
> + if (!strncmp(line, field, field_len)) {
> + strncpy(value, line, len);
> + ret = 0;
> + break;
> + }
> + } while (*line);
> +
> + fclose(f);
> +
> + return ret;
> +}
> +
> +static uint64_t get_host_cpu_model(void)
> +{
> + char line[512];
> + char *ns;
> + static uint64_t cpuid;
> +
> + if (cpuid) {
> + return cpuid;
> + }
> +
> + if (read_cpuinfo("Model Name", line, sizeof(line))) {
> + return 0;
> + }
> +
> + ns = strchr(line, ':');
> + if (!ns) {
> + return 0;
> + }
> +
> + ns = strstr(ns, "Loongson-");
> + if (!ns) {
> + return 0;
> + }
> +
> + ns += strlen("Loongson-");
> + memccpy((void *)&cpuid, ns, 0, 8);
> + return cpuid;
> +}
> +
> +static uint32_t get_host_cpucfg(int number)
> +{
> + unsigned int data = 0;
> +
> +#ifdef __loongarch__
> + asm volatile("cpucfg %[val], %[reg]"
> + : [val] "=r" (data)
> + : [reg] "r" (number)
> + : "memory");
> +#endif
> +
> + return data;
> +}
> +
> +static void loongarch_host_initfn(Object *obj)
> +{
> + uint32_t data;
> + uint64_t cpuid;
> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +
> + loongarch_max_initfn(obj);
> + data = get_host_cpucfg(0);
> + if (data) {
> + cpu->env.cpucfg[0] = data;
> + }
> +
Does the feature bit on cpucfg[2] also need to be consistent with the
host feature bit?
Otherwise, some features might be lost.
Thanks!
Xianglai.
> + cpuid = get_host_cpu_model();
> + if (cpuid) {
> + cpu->env.cpu_id = cpuid;
> + }
> +}
> +#endif
> +
> static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
> {
> uint8_t tlb_ps;
> @@ -780,6 +871,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
> DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
> DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
> DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
> +#if defined(CONFIG_KVM)
> + DEFINE_LOONGARCH_CPU_TYPE(64, "host", loongarch_host_initfn),
> +#endif
> };
>
> DEFINE_TYPES(loongarch_cpu_type_infos)
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode
2025-12-04 1:57 ` lixianglai
@ 2025-12-04 2:58 ` Bibo Mao
0 siblings, 0 replies; 6+ messages in thread
From: Bibo Mao @ 2025-12-04 2:58 UTC (permalink / raw)
To: lixianglai, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 2025/12/4 上午9:57, lixianglai wrote:
> Hi Bibo Mao:
>> Host CPU model is basically the same with max CPU model, except Product
>> ID and CPU model name. With host CPU model, Product ID comes from
>> cpucfg0 and CPU model comes from /proc/cpuinfo.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>> target/loongarch/cpu.c | 94 ++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index 8b8723a343..c7f52adeb9 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -429,6 +429,97 @@ static void loongarch_max_initfn(Object *obj)
>> }
>> }
>> +#if defined(CONFIG_KVM)
>> +static int read_cpuinfo(const char *field, char *value, int len)
>> +{
>> + FILE *f;
>> + int ret = -1;
>> + int field_len = strlen(field);
>> + char line[512];
>> +
>> + f = fopen("/proc/cpuinfo", "r");
>> + if (!f) {
>> + return -1;
>> + }
>> +
>> + do {
>> + if (!fgets(line, sizeof(line), f)) {
>> + break;
>> + }
>> + if (!strncmp(line, field, field_len)) {
>> + strncpy(value, line, len);
>> + ret = 0;
>> + break;
>> + }
>> + } while (*line);
>> +
>> + fclose(f);
>> +
>> + return ret;
>> +}
>> +
>> +static uint64_t get_host_cpu_model(void)
>> +{
>> + char line[512];
>> + char *ns;
>> + static uint64_t cpuid;
>> +
>> + if (cpuid) {
>> + return cpuid;
>> + }
>> +
>> + if (read_cpuinfo("Model Name", line, sizeof(line))) {
>> + return 0;
>> + }
>> +
>> + ns = strchr(line, ':');
>> + if (!ns) {
>> + return 0;
>> + }
>> +
>> + ns = strstr(ns, "Loongson-");
>> + if (!ns) {
>> + return 0;
>> + }
>> +
>> + ns += strlen("Loongson-");
>> + memccpy((void *)&cpuid, ns, 0, 8);
>> + return cpuid;
>> +}
>> +
>> +static uint32_t get_host_cpucfg(int number)
>> +{
>> + unsigned int data = 0;
>> +
>> +#ifdef __loongarch__
>> + asm volatile("cpucfg %[val], %[reg]"
>> + : [val] "=r" (data)
>> + : [reg] "r" (number)
>> + : "memory");
>> +#endif
>> +
>> + return data;
>> +}
>> +
>> +static void loongarch_host_initfn(Object *obj)
>> +{
>> + uint32_t data;
>> + uint64_t cpuid;
>> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
>> +
>> + loongarch_max_initfn(obj);
>> + data = get_host_cpucfg(0);
>> + if (data) {
>> + cpu->env.cpucfg[0] = data;
>> + }
>> +
>
> Does the feature bit on cpucfg[2] also need to be consistent with the
> host feature bit?
> Otherwise, some features might be lost.
well, will check the detailed bits with CPUCFG2 in next version.
bit10 LVZ will be disabled since nested KVM is not supported
bit18-20/bit24 deeps on whether it is supported on KVM host and QEMU
bit25-30 atomic instruction should be the same with host, it is
irrelative with KVM.
Regards
Bibo Mao
>
> Thanks!
> Xianglai.
>
>
>> + cpuid = get_host_cpu_model();
>> + if (cpuid) {
>> + cpu->env.cpu_id = cpuid;
>> + }
>> +}
>> +#endif
>> +
>> static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
>> {
>> uint8_t tlb_ps;
>> @@ -780,6 +871,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
>> DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
>> DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
>> DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
>> +#if defined(CONFIG_KVM)
>> + DEFINE_LOONGARCH_CPU_TYPE(64, "host", loongarch_host_initfn),
>> +#endif
>> };
>> DEFINE_TYPES(loongarch_cpu_type_infos)
^ permalink raw reply [flat|nested] 6+ messages in thread