From: Richard Henderson <richard.henderson@linaro.org>
To: Jinjie Ruan <ruanjinjie@huawei.com>,
peter.maydell@linaro.org, eduardo@habkost.net,
marcel.apfelbaum@gmail.com, philmd@linaro.org,
wangyanan55@huawei.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: Re: [RFC PATCH v2 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI
Date: Wed, 21 Feb 2024 11:36:32 -1000 [thread overview]
Message-ID: <edbe3faa-d83e-4410-811a-d15fe244817a@linaro.org> (raw)
In-Reply-To: <20240221130823.677762-9-ruanjinjie@huawei.com>
On 2/21/24 03:08, Jinjie Ruan via wrote:
> Add IS and FS bit in ISR_EL1 and handle the read according to whether the
> NMI is IRQ or FIQ.
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
> target/arm/cpu.h | 2 ++
> target/arm/helper.c | 9 +++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 051e589e19..e2d07e3312 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1476,6 +1476,8 @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
> #define CPSR_N (1U << 31)
> #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
> #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
> +#define ISR_FS (1U << 9)
> +#define ISR_IS (1U << 10)
>
> #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
> #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 0bd7a87e51..62c8e5d611 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2022,6 +2022,10 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> ret |= CPSR_I;
> }
> +
> + if ((cs->interrupt_request & CPU_INTERRUPT_NMI) && env->nmi_is_irq) {
> + ret |= ISR_IS;
> + }
> }
>
> if (hcr_el2 & HCR_FMO) {
> @@ -2032,6 +2036,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
> ret |= CPSR_F;
> }
> +
> + if ((cs->interrupt_request & CPU_INTERRUPT_NMI) &&
> + (!env->nmi_is_irq)) {
> + ret |= ISR_FS;
> + }
> }
The external CPU_INTERRUPT_NMI will never signal FIQ.
With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set.
Missing is the handling of HCRX_EL2.{VFNMI,VINMI} to signal vFIQ and vIRQ with
superpriority. Unless I missed it, I don't see HCRX_EL2 adjusted for FEAT_NMI at all.
r~
next prev parent reply other threads:[~2024-02-21 21:37 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 13:08 [RFC PATCH v2 00/22] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 01/22] target/arm: Add FEAT_NMI to max Jinjie Ruan via
2024-02-21 21:22 ` Richard Henderson
2024-02-22 1:52 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 02/22] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Jinjie Ruan via
2024-02-21 18:28 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 03/22] target/arm: Add PSTATE.ALLINT Jinjie Ruan via
2024-02-21 18:50 ` Richard Henderson
2024-02-22 1:48 ` Jinjie Ruan via
2024-02-22 19:25 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 04/22] target/arm: Implement ALLINT MSR (immediate) Jinjie Ruan via
2024-02-21 19:09 ` Richard Henderson
2024-02-21 19:17 ` Richard Henderson
2024-02-21 20:41 ` Richard Henderson
2024-02-22 2:40 ` Jinjie Ruan via
2024-02-22 19:42 ` Richard Henderson
2024-02-22 2:34 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT Jinjie Ruan via
2024-02-21 19:28 ` Richard Henderson
2024-02-22 3:50 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 06/22] target/arm: Add support for Non-maskable Interrupt Jinjie Ruan via
2024-02-21 20:06 ` Richard Henderson
2024-02-22 2:44 ` Jinjie Ruan via
2024-02-22 9:27 ` Jinjie Ruan via
2024-02-21 21:23 ` Richard Henderson
2024-02-22 9:26 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 07/22] target/arm: Add support for NMI event state Jinjie Ruan via
2024-02-21 20:10 ` Richard Henderson
2024-02-21 21:25 ` Richard Henderson
2024-02-22 11:52 ` Jinjie Ruan via
2024-02-22 18:38 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI Jinjie Ruan via
2024-02-21 21:36 ` Richard Henderson [this message]
2024-02-22 12:34 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 09/22] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Jinjie Ruan via
2024-02-21 20:16 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 10/22] target/arm: Handle PSTATE.ALLINT on taking an exception Jinjie Ruan via
2024-02-21 20:36 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 11/22] target/arm: Set pstate.ALLINT in arm_cpu_reset_hold Jinjie Ruan via
2024-02-21 20:43 ` Richard Henderson
2024-02-22 12:48 ` Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 12/22] hw/arm/virt: Wire NMI irq line from GIC to CPU Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 13/22] hw/intc/arm_gicv3: Add external IRQ lines for NMI Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 14/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 15/22] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Jinjie Ruan via
2024-02-21 20:48 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 16/22] hw/intc/arm_gicv3: Implement GICD_INMIR Jinjie Ruan via
2024-02-21 21:44 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 17/22] hw/intc: Enable FEAT_GICv3_NMI Feature Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 18/22] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC Jinjie Ruan via
2024-02-21 21:47 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 19/22] hw/intc/arm_gicv3: Add irq superpriority information Jinjie Ruan via
2024-02-21 21:48 ` Richard Henderson
2024-02-21 13:08 ` [RFC PATCH v2 20/22] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 21/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty Jinjie Ruan via
2024-02-21 13:08 ` [RFC PATCH v2 22/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Jinjie Ruan via
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