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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id u2-20020a17090282c200b001dbcf653017sm7878074plz.289.2024.02.21.13.36.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Feb 2024 13:36:35 -0800 (PST) Message-ID: Date: Wed, 21 Feb 2024 11:36:32 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI Content-Language: en-US To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240221130823.677762-1-ruanjinjie@huawei.com> <20240221130823.677762-9-ruanjinjie@huawei.com> From: Richard Henderson In-Reply-To: <20240221130823.677762-9-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/21/24 03:08, Jinjie Ruan via wrote: > Add IS and FS bit in ISR_EL1 and handle the read according to whether the > NMI is IRQ or FIQ. > > Signed-off-by: Jinjie Ruan > --- > target/arm/cpu.h | 2 ++ > target/arm/helper.c | 9 +++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 051e589e19..e2d07e3312 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1476,6 +1476,8 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) > #define CPSR_N (1U << 31) > #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) > #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) > +#define ISR_FS (1U << 9) > +#define ISR_IS (1U << 10) > > #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) > #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0bd7a87e51..62c8e5d611 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2022,6 +2022,10 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) > if (cs->interrupt_request & CPU_INTERRUPT_HARD) { > ret |= CPSR_I; > } > + > + if ((cs->interrupt_request & CPU_INTERRUPT_NMI) && env->nmi_is_irq) { > + ret |= ISR_IS; > + } > } > > if (hcr_el2 & HCR_FMO) { > @@ -2032,6 +2036,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) > if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { > ret |= CPSR_F; > } > + > + if ((cs->interrupt_request & CPU_INTERRUPT_NMI) && > + (!env->nmi_is_irq)) { > + ret |= ISR_FS; > + } > } The external CPU_INTERRUPT_NMI will never signal FIQ. With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. Missing is the handling of HCRX_EL2.{VFNMI,VINMI} to signal vFIQ and vIRQ with superpriority. Unless I missed it, I don't see HCRX_EL2 adjusted for FEAT_NMI at all. r~