From: Eric Auger <eric.auger@redhat.com>
To: Wang Xingang <wangxingang5@huawei.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
shannon.zhaosl@gmail.com, imammedo@redhat.com, mst@redhat.com,
marcel.apfelbaum@gmail.com, peter.maydell@linaro.org,
ehabkost@redhat.com, richard.henderson@linaro.org,
pbonzini@redhat.com
Cc: xieyingtai@huawei.com
Subject: Re: [PATCH v4 5/8] hw/pci: Add pci_bus_range to get bus number range
Date: Wed, 2 Jun 2021 15:03:00 +0200 [thread overview]
Message-ID: <edcf80ec-7f91-b986-047c-a87c8cc7d669@redhat.com> (raw)
In-Reply-To: <1621914605-14724-6-git-send-email-wangxingang5@huawei.com>
Hi Xingang,
On 5/25/21 5:50 AM, Wang Xingang wrote:
> From: Xingang Wang <wangxingang5@huawei.com>
>
> This helps to get the bus number range of a pci bridge hierarchy.
>
> Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
> ---
> hw/pci/pci.c | 15 +++++++++++++++
> include/hw/pci/pci.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 27d588e268..7f18ea5ef5 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -537,6 +537,21 @@ int pci_bus_num(PCIBus *s)
> return PCI_BUS_GET_CLASS(s)->bus_num(s);
> }
>
Add a doc comment such as "returns the min and max bus numbers of a root
bus"?
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Thanks
Eric
> +void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus)
> +{
> + int i;
> + *min_bus = *max_bus = pci_bus_num(bus);
> +
> + for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
> + PCIDevice *dev = bus->devices[i];
> +
> + if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
> + *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]);
> + *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]);
> + }
> + }
> +}
> +
> int pci_bus_numa_node(PCIBus *bus)
> {
> return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index f4d51b672b..d0f4266e37 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -450,6 +450,7 @@ static inline PCIBus *pci_get_bus(const PCIDevice *dev)
> return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
> }
> int pci_bus_num(PCIBus *s);
> +void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
> static inline int pci_dev_bus_num(const PCIDevice *dev)
> {
> return pci_bus_num(pci_get_bus(dev));
next prev parent reply other threads:[~2021-06-02 13:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-25 3:49 [PATCH v4 0/8] IOMMU: Add support for IOMMU Bypass Feature Wang Xingang
2021-05-25 3:49 ` [PATCH v4 1/8] hw/pci/pci_host: Allow bypass iommu for pci host Wang Xingang
2021-06-02 12:18 ` Eric Auger
2021-06-03 12:42 ` Xingang Wang
2021-05-25 3:49 ` [PATCH v4 2/8] hw/pxb: Add a bypass iommu property Wang Xingang
2021-06-02 12:18 ` Eric Auger
2021-05-25 3:50 ` [PATCH v4 3/8] hw/arm/virt: Add a machine option to bypass iommu for primary bus Wang Xingang
2021-06-02 12:25 ` Eric Auger
2021-06-03 12:47 ` Xingang Wang
2021-05-25 3:50 ` [PATCH v4 4/8] hw/i386: Add a pc " Wang Xingang
2021-05-25 3:50 ` [PATCH v4 5/8] hw/pci: Add pci_bus_range to get bus number range Wang Xingang
2021-06-02 13:03 ` Eric Auger [this message]
2021-06-03 12:48 ` Xingang Wang
2021-05-25 3:50 ` [PATCH v4 6/8] hw/arm/virt-acpi-build: Add explicit IORT idmap for smmuv3 node Wang Xingang
2021-06-02 14:21 ` Eric Auger
2021-06-03 12:52 ` Xingang Wang
2021-05-25 3:50 ` [PATCH v4 7/8] hw/i386/acpi-build: Add explicit scope in DMAR table Wang Xingang
2021-05-25 3:50 ` [PATCH v4 8/8] hw/i386/acpi-build: Add bypass_iommu check when building IVRS table Wang Xingang
2021-05-31 11:38 ` [PATCH v4 0/8] IOMMU: Add support for IOMMU Bypass Feature Xingang Wang
2021-06-05 12:32 ` Igor Mammedov
2021-06-08 12:24 ` Xingang Wang
2021-06-08 13:38 ` Igor Mammedov
2021-06-15 12:04 ` Xingang Wang
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