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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id f18sm481151pga.75.2020.06.01.17.01.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jun 2020 17:01:54 -0700 (PDT) Subject: Re: [PATCH 5/6] exec: Restrict 32-bit CPUs to 32-bit address space To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell References: <20200531175425.10329-1-f4bug@amsat.org> <20200531175425.10329-6-f4bug@amsat.org> <2e78619d-543b-55b7-f241-7652274fcf4a@amsat.org> From: Richard Henderson Message-ID: Date: Mon, 1 Jun 2020 17:01:52 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <2e78619d-543b-55b7-f241-7652274fcf4a@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , David Hildenbrand , Cornelia Huck , QEMU Developers , Beniamino Galvani , qemu-s390x , qemu-arm , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Gerd Hoffmann , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/1/20 1:09 AM, Philippe Mathieu-Daudé wrote: > On 5/31/20 9:09 PM, Peter Maydell wrote: >> On Sun, 31 May 2020 at 18:54, Philippe Mathieu-Daudé wrote: >>> >>> It is pointless to have 32-bit CPUs see a 64-bit address >>> space, when they can only address the 32 lower bits. >>> >>> Only create CPU address space with a size it can address. >>> This makes HMP 'info mtree' command easier to understand >>> (on 32-bit CPUs). >> >>> diff --git a/exec.c b/exec.c >>> index 5162f0d12f..d6809a9447 100644 >>> --- a/exec.c >>> +++ b/exec.c >>> @@ -2962,9 +2962,17 @@ static void tcg_commit(MemoryListener *listener) >>> >>> static void memory_map_init(void) >>> { >>> + uint64_t system_memory_size; >>> + >>> +#if TARGET_LONG_BITS >= 64 >>> + system_memory_size = UINT64_MAX; >>> +#else >>> + system_memory_size = 1ULL << TARGET_LONG_BITS; >>> +#endif >> >> TARGET_LONG_BITS is a description of the CPU's virtual >> address size; but the size of the system_memory memory >> region is related to the CPU's physical address size[*]. > > OK I misunderstood it was the physical size, not virtual. It is the physical size. In the armv7 case, the lpae page table entry maps a 32-bit virtual address to a 40-bit physical address. The i686 page table extensions do something similar. See TARGET_PHYS_ADDR_SPACE_BITS. r~