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Tue, 18 Mar 2025 19:45:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGFBS7253tJjnD2/zEGjrm6mRBaZ4jJE72SANf9JYB0efkeDEfeBRAvg8j0RG3j6GEQycorDA== X-Received: by 2002:a05:6602:3a0a:b0:85b:3e32:9afb with SMTP id ca18e2360f4ac-85e138a678emr154257939f.14.1742352343293; Tue, 18 Mar 2025 19:45:43 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-85db8777bf0sm293160339f.13.2025.03.18.19.45.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Mar 2025 19:45:42 -0700 (PDT) Message-ID: Date: Tue, 18 Mar 2025 22:45:39 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 16/20] hw/arm/smmuv3-accel: Read host SMMUv3 device info Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: eric.auger@redhat.com, peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-17-shameerali.kolothum.thodi@huawei.com> From: Donald Dutile In-Reply-To: <20250311141045.66620-17-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=ddutile@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.332, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Shameer, Hey, On 3/11/25 10:10 AM, Shameer Kolothum wrote: > From: Nicolin Chen > > Read the underlying SMMUv3 device info and set corresponding IDR > bits. We need at least one cold-plugged vfio-pci dev associated > with the smmuv3-accel instance to do this now.  Hence fail if it > is not available. > > ToDo: The above requirement will be relaxed in future when we add > support in the kernel. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 104 ++++++++++++++++++++++++++++++++++ > hw/arm/trace-events | 1 + > include/hw/arm/smmuv3-accel.h | 2 + > 3 files changed, 107 insertions(+) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 09be838d22..fb08e1d66b 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -15,6 +15,96 @@ > > #include "smmuv3-internal.h" > > +static int > +smmuv3_accel_dev_get_info(SMMUv3AccelDevice *accel_dev, uint32_t *data_type, > + uint32_t data_len, void *data) > +{ > + uint64_t caps; > + > + if (!accel_dev || !accel_dev->idev) { > + return -ENOENT; > + } > + > + return !iommufd_backend_get_device_info(accel_dev->idev->iommufd, > + accel_dev->idev->devid, > + data_type, data, > + data_len, &caps, NULL); > +} > + > +static void smmuv3_accel_init_regs(SMMUv3AccelState *s_accel) > +{ > + SMMUv3State *s = ARM_SMMUV3(s_accel); > + SMMUv3AccelDevice *accel_dev; > + uint32_t data_type; > + uint32_t val; > + int ret; > + > + if (!s_accel->viommu || QLIST_EMPTY(&s_accel->viommu->device_list)) { > + error_report("At least one cold-plugged vfio-pci is required for smmuv3-accel!"); > + exit(1); > + } > + > + accel_dev = QLIST_FIRST(&s_accel->viommu->device_list); > + if (accel_dev->info.idr[0]) { > + info_report("reusing the previous hw_info"); > + goto out; > + } > + > + ret = smmuv3_accel_dev_get_info(accel_dev, &data_type, > + sizeof(accel_dev->info), &accel_dev->info); > + if (ret) { > + error_report("failed to get SMMU device info"); > + return; > + } > + > + if (data_type != IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { > + error_report("Wrong data type (%d)!", data_type); > + return; > + } > + > +out: > + trace_smmuv3_accel_get_device_info(accel_dev->info.idr[0], > + accel_dev->info.idr[1], > + accel_dev->info.idr[3], > + accel_dev->info.idr[5]); > + > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, BTM); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, BTM, val); > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, ATS); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, val); > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, ASID16); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, val); > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, TERM_MODEL); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, val); > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, STALL_MODEL); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, val); > + val = FIELD_EX32(accel_dev->info.idr[0], IDR0, STLEVEL); > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, val); > + > + val = FIELD_EX32(accel_dev->info.idr[1], IDR1, SIDSIZE); > + s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, val); > + val = FIELD_EX32(accel_dev->info.idr[1], IDR1, SSIDSIZE); > + s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, val); > + > + val = FIELD_EX32(accel_dev->info.idr[3], IDR3, HAD); > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, val); > + val = FIELD_EX32(accel_dev->info.idr[3], IDR3, RIL); > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, val); > + val = FIELD_EX32(accel_dev->info.idr[3], IDR3, BBML); > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, val); > + > + val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN4K); > + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, val); > + val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN16K); > + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, val); > + val = FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN64K); > + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, val); > + val = FIELD_EX32(accel_dev->info.idr[5], IDR5, OAS); > + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, val); > + > + /* FIXME check iidr and aidr registrs too */ > +} > + > static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *sbus, > PCIBus *bus, int devfn) > { > @@ -484,11 +574,25 @@ static void smmu_accel_realize(DeviceState *d, Error **errp) > bs->unset_iommu_device = smmuv3_accel_unset_iommu_device; > } > > +static void smmuv3_accel_reset_hold(Object *obj, ResetType type) > +{ > + SMMUv3AccelState *s = ARM_SMMUV3_ACCEL(obj); > + SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_GET_CLASS(s); > + > + if (c->parent_phases.hold) { > + c->parent_phases.hold(obj, type); > + } > + smmuv3_accel_init_regs(s); > +} reset has to be moved from hold to exit phase.... Eric recently posted a fix for this issue in upstream. ... and if accel was just a feature of the common smmuv3 support, this reset wouldn't be needed... > + > static void smmuv3_accel_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_CLASS(klass); > > + resettable_class_set_parent_phases(rc, NULL, smmuv3_accel_reset_hold, NULL, > + &c->parent_phases); > device_class_set_parent_realize(dc, smmu_accel_realize, > &c->parent_realize); > dc->hotpluggable = false; > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index cd2eac31c2..c7a7e58291 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -62,6 +62,7 @@ smmu_reset_exit(void) "" > smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=0x%x (sid=0x%x)" > smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=0x%x (sid=0x%x" > smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste_0) "sid=%d ste=%"PRIx64":%"PRIx64 > +smmuv3_accel_get_device_info(uint32_t idr0, uint32_t idr1, uint32_t idr3, uint32_t idr5) "idr0=0x%x idr1=0x%x idr3=0x%x idr5=0x%x" > > # strongarm.c > strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" > diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h > index 58e68534c0..9e30d7d351 100644 > --- a/include/hw/arm/smmuv3-accel.h > +++ b/include/hw/arm/smmuv3-accel.h > @@ -52,6 +52,7 @@ typedef struct SMMUv3AccelDevice { > SMMUViommu *viommu; > SMMUVdev *vdev; > AddressSpace as_sysmem; > + struct iommu_hw_info_arm_smmuv3 info; > QLIST_ENTRY(SMMUv3AccelDevice) next; > } SMMUv3AccelDevice; > > @@ -68,6 +69,7 @@ struct SMMUv3AccelClass { > /*< public >*/ > > DeviceRealize parent_realize; > + ResettablePhases parent_phases; > }; > > #endif /* HW_ARM_SMMUV3_ACCEL_H */ In general, I would move this common code stuff at the front of the patch series... just gathering registers, capabilities, etc. - Don