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From: "mar.krzeminski" <mar.krzeminski@gmail.com>
To: Jean-Christophe DUBOIS <jcd@tribudubois.net>,
	qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access.
Date: Fri, 6 Jan 2017 19:48:51 +0100	[thread overview]
Message-ID: <ee0812b8-e416-6fb8-82c1-f0b07cb1a348@gmail.com> (raw)
In-Reply-To: <d4cf5c4e-499f-c99e-edde-6df0e7bf059b@tribudubois.net>



W dniu 06.01.2017 o 19:18, Jean-Christophe DUBOIS pisze:
> Le 06/01/2017 à 13:28, mar.krzeminski a écrit :
>>>> Please make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's 
>>>> after reset/power up (defaults).
>>>
>>> There is already a memset to 0 of all regs (including CONFIGREG) in 
>>> the reset function.
>> I saw that memset, my question is rather real HW also have 0s after 
>> reset (could be important
>> in some cases).
>
> Yes, all registers are set to 0 at reset except STATREG which is set 
> to 3 (according to reference manual).
>
Thanks!
>>
>> Thanks,
>> Marcin
>
>

      reply	other threads:[~2017-01-06 18:48 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-03 20:35 [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access Jean-Christophe Dubois
2017-01-04 20:56 ` mar.krzeminski
2017-01-04 21:54   ` Jean-Christophe DUBOIS
2017-01-06 12:28     ` mar.krzeminski
2017-01-06 18:18       ` Jean-Christophe DUBOIS
2017-01-06 18:48         ` mar.krzeminski [this message]

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