Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500

[Jiaxun Yang <jiaxun.yang@flygoat.com>]

在 2023/6/30 15:28, Marcin Nowakowski 写道:
> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
> so indicate that properly in CP0.Config5 register bits [16:15].
>
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>

VZ is unimplemented in TCG so perhaps we should leave them as not supported?

Thanks
- Jiaxun

> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index d45f245a67..da122e72d7 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -709,7 +709,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
>                          (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
>           .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
> -                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
> +                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
>           .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
>                                     (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
>           .CP0_LLAddr_rw_bitmask = 0,
> @@ -749,7 +749,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
>                          (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
>           .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
> -                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
> +                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
>           .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
>                                     (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
>           .CP0_LLAddr_rw_bitmask = 0,