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Mon, 10 Jul 2023 08:58:23 -0400 (EDT) Message-ID: Date: Mon, 10 Jul 2023 20:58:21 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500 To: Marcin Nowakowski , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Aurelien Jarno , Aleksandar Rikalo , "open list:All patches CC here" References: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> From: Jiaxun Yang In-Reply-To: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=64.147.123.21; envelope-from=jiaxun.yang@flygoat.com; helo=wout5-smtp.messagingengine.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 在 2023/6/30 15:28, Marcin Nowakowski 写道: > GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, > so indicate that properly in CP0.Config5 register bits [16:15]. > > Signed-off-by: Marcin Nowakowski VZ is unimplemented in TCG so perhaps we should leave them as not supported? Thanks - Jiaxun > --- > target/mips/cpu-defs.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc > index d45f245a67..da122e72d7 100644 > --- a/target/mips/cpu-defs.c.inc > +++ b/target/mips/cpu-defs.c.inc > @@ -709,7 +709,7 @@ const mips_def_t mips_defs[] = > .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | > (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), > .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | > - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), > + (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI), > .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | > (1 << CP0C5_FRE) | (1 << CP0C5_UFE), > .CP0_LLAddr_rw_bitmask = 0, > @@ -749,7 +749,7 @@ const mips_def_t mips_defs[] = > .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | > (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), > .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | > - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), > + (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI), > .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | > (1 << CP0C5_FRE) | (1 << CP0C5_UFE), > .CP0_LLAddr_rw_bitmask = 0,