From: Jay Foad <jay.foad@gmail.com>
To: qemu-devel@nongnu.org
Cc: Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
Date: Mon, 22 Feb 2010 15:53:55 +0000 [thread overview]
Message-ID: <ee2e06e91002220753l3e3848d7q6afb99adeabc510e@mail.gmail.com> (raw)
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>
---
tcg/hppa/tcg-target.c | 1 -
tcg/ppc/tcg-target.c | 2 --
tcg/sparc/tcg-target.c | 4 ++++
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index ddce60c..4677971 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
{ INDEX_op_qemu_st8, { "L", "L", "L" } },
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 903b69f..15d8b85 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
{ INDEX_op_qemu_st8, { "K", "K" } },
@@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
{ INDEX_op_qemu_st8, { "K", "K", "K" } },
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 891b8c4..d4ddaa7 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s,
int opc, const TCGArg *args,
case INDEX_op_qemu_ld32u:
tcg_out_qemu_ld(s, args, 2);
break;
+#if TCG_TARGET_REG_BITS == 64
case INDEX_op_qemu_ld32s:
tcg_out_qemu_ld(s, args, 2 | 4);
break;
+#endif
case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0);
break;
@@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
+#if TCG_TARGET_REG_BITS == 64
{ INDEX_op_qemu_ld32s, { "r", "L" } },
+#endif
{ INDEX_op_qemu_st8, { "L", "L" } },
{ INDEX_op_qemu_st16, { "L", "L" } },
next reply other threads:[~2010-02-22 15:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-22 15:53 Jay Foad [this message]
2010-02-22 16:35 ` [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts Stefan Weil
2010-02-22 16:37 ` Jay Foad
2010-02-22 16:58 ` Stefan Weil
2010-03-03 22:06 ` Stuart Brady
2010-02-22 16:42 ` malc
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