From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Njabe-0005fb-LH for qemu-devel@nongnu.org; Mon, 22 Feb 2010 10:53:58 -0500 Received: from [199.232.76.173] (port=60278 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Njabe-0005fT-6O for qemu-devel@nongnu.org; Mon, 22 Feb 2010 10:53:58 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Njabd-0007ce-CQ for qemu-devel@nongnu.org; Mon, 22 Feb 2010 10:53:57 -0500 Received: from mail-bw0-f218.google.com ([209.85.218.218]:65424) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Njabd-0007cW-1Y for qemu-devel@nongnu.org; Mon, 22 Feb 2010 10:53:57 -0500 Received: by bwz10 with SMTP id 10so1754926bwz.2 for ; Mon, 22 Feb 2010 07:53:55 -0800 (PST) MIME-Version: 1.0 Date: Mon, 22 Feb 2010 15:53:55 +0000 Message-ID: From: Jay Foad Content-Type: text/plain; charset=ISO-8859-1 Subject: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexander Graf The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad --- tcg/hppa/tcg-target.c | 1 - tcg/ppc/tcg-target.c | 2 -- tcg/sparc/tcg-target.c | 4 ++++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c index ddce60c..4677971 100644 --- a/tcg/hppa/tcg-target.c +++ b/tcg/hppa/tcg-target.c @@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, { INDEX_op_qemu_st8, { "L", "L", "L" } }, diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 903b69f..15d8b85 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L" } }, { INDEX_op_qemu_st8, { "K", "K" } }, @@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } }, { INDEX_op_qemu_st8, { "K", "K", "K" } }, diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 891b8c4..d4ddaa7 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_qemu_ld32u: tcg_out_qemu_ld(s, args, 2); break; +#if TCG_TARGET_REG_BITS == 64 case INDEX_op_qemu_ld32s: tcg_out_qemu_ld(s, args, 2 | 4); break; +#endif case INDEX_op_qemu_st8: tcg_out_qemu_st(s, args, 0); break; @@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, +#if TCG_TARGET_REG_BITS == 64 { INDEX_op_qemu_ld32s, { "r", "L" } }, +#endif { INDEX_op_qemu_st8, { "L", "L" } }, { INDEX_op_qemu_st16, { "L", "L" } },