* [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
@ 2010-02-22 15:53 Jay Foad
2010-02-22 16:35 ` Stefan Weil
2010-02-22 16:42 ` malc
0 siblings, 2 replies; 6+ messages in thread
From: Jay Foad @ 2010-02-22 15:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Graf
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>
---
tcg/hppa/tcg-target.c | 1 -
tcg/ppc/tcg-target.c | 2 --
tcg/sparc/tcg-target.c | 4 ++++
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index ddce60c..4677971 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
{ INDEX_op_qemu_st8, { "L", "L", "L" } },
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 903b69f..15d8b85 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L" } },
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
{ INDEX_op_qemu_st8, { "K", "K" } },
@@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
{ INDEX_op_qemu_st8, { "K", "K", "K" } },
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 891b8c4..d4ddaa7 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s,
int opc, const TCGArg *args,
case INDEX_op_qemu_ld32u:
tcg_out_qemu_ld(s, args, 2);
break;
+#if TCG_TARGET_REG_BITS == 64
case INDEX_op_qemu_ld32s:
tcg_out_qemu_ld(s, args, 2 | 4);
break;
+#endif
case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0);
break;
@@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld16s, { "r", "L" } },
{ INDEX_op_qemu_ld32u, { "r", "L" } },
+#if TCG_TARGET_REG_BITS == 64
{ INDEX_op_qemu_ld32s, { "r", "L" } },
+#endif
{ INDEX_op_qemu_st8, { "L", "L" } },
{ INDEX_op_qemu_st16, { "L", "L" } },
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
2010-02-22 15:53 [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts Jay Foad
@ 2010-02-22 16:35 ` Stefan Weil
2010-02-22 16:37 ` Jay Foad
2010-03-03 22:06 ` Stuart Brady
2010-02-22 16:42 ` malc
1 sibling, 2 replies; 6+ messages in thread
From: Stefan Weil @ 2010-02-22 16:35 UTC (permalink / raw)
To: Jay Foad; +Cc: qemu-devel, Alexander Graf
Jay Foad schrieb:
> The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
>
> Signed-off-by: Jay Foad <jay.foad@gmail.com>
> ---
> tcg/hppa/tcg-target.c | 1 -
> tcg/ppc/tcg-target.c | 2 --
> tcg/sparc/tcg-target.c | 4 ++++
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
> index ddce60c..4677971 100644
> --- a/tcg/hppa/tcg-target.c
> +++ b/tcg/hppa/tcg-target.c
> @@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = {
> { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
> { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
> { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
> - { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
> { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
>
> { INDEX_op_qemu_st8, { "L", "L", "L" } },
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 903b69f..15d8b85 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
> { INDEX_op_qemu_ld16u, { "r", "L" } },
> { INDEX_op_qemu_ld16s, { "r", "L" } },
> { INDEX_op_qemu_ld32u, { "r", "L" } },
> - { INDEX_op_qemu_ld32s, { "r", "L" } },
>
No. As I wrote in the original thread,
conditional compilation is needed here
(or you will get new compile errors).
> { INDEX_op_qemu_ld64, { "r", "r", "L" } },
>
> { INDEX_op_qemu_st8, { "K", "K" } },
> @@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
> { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
> { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
> { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
> - { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
>
dto.
> { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
>
> { INDEX_op_qemu_st8, { "K", "K", "K" } },
> diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
> index 891b8c4..d4ddaa7 100644
> --- a/tcg/sparc/tcg-target.c
> +++ b/tcg/sparc/tcg-target.c
> @@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s,
> int opc, const TCGArg *args,
> case INDEX_op_qemu_ld32u:
> tcg_out_qemu_ld(s, args, 2);
> break;
> +#if TCG_TARGET_REG_BITS == 64
> case INDEX_op_qemu_ld32s:
> tcg_out_qemu_ld(s, args, 2 | 4);
> break;
> +#endif
> case INDEX_op_qemu_st8:
> tcg_out_qemu_st(s, args, 0);
> break;
> @@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
> { INDEX_op_qemu_ld16u, { "r", "L" } },
> { INDEX_op_qemu_ld16s, { "r", "L" } },
> { INDEX_op_qemu_ld32u, { "r", "L" } },
> +#if TCG_TARGET_REG_BITS == 64
> { INDEX_op_qemu_ld32s, { "r", "L" } },
> +#endif
>
> { INDEX_op_qemu_st8, { "L", "L" } },
> { INDEX_op_qemu_st16, { "L", "L" } },
>
>
>
>
Maybe my comment applies also to the change in
tcg/hppa/tcg-target.c, but I tested only ppc
(using cross compilation).
Regards,
Stefan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
2010-02-22 16:35 ` Stefan Weil
@ 2010-02-22 16:37 ` Jay Foad
2010-02-22 16:58 ` Stefan Weil
2010-03-03 22:06 ` Stuart Brady
1 sibling, 1 reply; 6+ messages in thread
From: Jay Foad @ 2010-02-22 16:37 UTC (permalink / raw)
To: Stefan Weil; +Cc: qemu-devel, Alexander Graf
>> --- a/tcg/ppc/tcg-target.c
>> +++ b/tcg/ppc/tcg-target.c
>> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>> { INDEX_op_qemu_ld16u, { "r", "L" } },
>> { INDEX_op_qemu_ld16s, { "r", "L" } },
>> { INDEX_op_qemu_ld32u, { "r", "L" } },
>> - { INDEX_op_qemu_ld32s, { "r", "L" } },
>>
>
> No. As I wrote in the original thread,
> conditional compilation is needed here
> (or you will get new compile errors).
In tcg/ppc/, TCG_TARGET_REG_BITS is always 32, isn't it?
Thanks,
Jay.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
2010-02-22 15:53 [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts Jay Foad
2010-02-22 16:35 ` Stefan Weil
@ 2010-02-22 16:42 ` malc
1 sibling, 0 replies; 6+ messages in thread
From: malc @ 2010-02-22 16:42 UTC (permalink / raw)
To: Jay Foad; +Cc: qemu-devel, Alexander Graf
On Mon, 22 Feb 2010, Jay Foad wrote:
> The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Your mail client mangled the patch.
[..snip..]
> @@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s,
> int opc, const TCGArg *args,
Here.
[..snip..]
Fixed and applied.
--
mailto:av1474@comtv.ru
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
2010-02-22 16:37 ` Jay Foad
@ 2010-02-22 16:58 ` Stefan Weil
0 siblings, 0 replies; 6+ messages in thread
From: Stefan Weil @ 2010-02-22 16:58 UTC (permalink / raw)
To: Jay Foad; +Cc: qemu-devel, Alexander Graf
Jay Foad schrieb:
>>> --- a/tcg/ppc/tcg-target.c
>>> +++ b/tcg/ppc/tcg-target.c
>>> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>>> { INDEX_op_qemu_ld16u, { "r", "L" } },
>>> { INDEX_op_qemu_ld16s, { "r", "L" } },
>>> { INDEX_op_qemu_ld32u, { "r", "L" } },
>>> - { INDEX_op_qemu_ld32s, { "r", "L" } },
>>>
>>>
>> No. As I wrote in the original thread,
>> conditional compilation is needed here
>> (or you will get new compile errors).
>>
>
> In tcg/ppc/, TCG_TARGET_REG_BITS is always 32, isn't it?
>
> Thanks,
> Jay.
>
Yes, you are right. Please excuse my wrong feedback.
Stefan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts
2010-02-22 16:35 ` Stefan Weil
2010-02-22 16:37 ` Jay Foad
@ 2010-03-03 22:06 ` Stuart Brady
1 sibling, 0 replies; 6+ messages in thread
From: Stuart Brady @ 2010-03-03 22:06 UTC (permalink / raw)
To: qemu-devel
On Mon, Feb 22, 2010 at 05:35:16PM +0100, Stefan Weil wrote:
> Maybe my comment applies also to the change in
> tcg/hppa/tcg-target.c, but I tested only ppc
> (using cross compilation).
HPPA host support is 32-bit only for the time being, as there isn't even
a 64-bit userspace for HPPA, yet, and that's unlikely to change soon.
--
Cheers,
Stuart Brady
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-03-03 22:08 UTC | newest]
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2010-02-22 15:53 [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc hosts Jay Foad
2010-02-22 16:35 ` Stefan Weil
2010-02-22 16:37 ` Jay Foad
2010-02-22 16:58 ` Stefan Weil
2010-03-03 22:06 ` Stuart Brady
2010-02-22 16:42 ` malc
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