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Date: Mon, 22 Feb 2010 16:37:58 +0000
Message-ID: <ee2e06e91002220837v3268c0c6ieb509ca862f143e5@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] tcg: fix build on 32-bit hppa, ppc and sparc
	hosts
From: Jay Foad <jay.foad@gmail.com>
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To: Stefan Weil <weil@mail.berlios.de>
Cc: qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>

>> --- a/tcg/ppc/tcg-target.c
>> +++ b/tcg/ppc/tcg-target.c
>> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] =3D {
>> =A0 =A0 =A0{ INDEX_op_qemu_ld16u, { "r", "L" } },
>> =A0 =A0 =A0{ INDEX_op_qemu_ld16s, { "r", "L" } },
>> =A0 =A0 =A0{ INDEX_op_qemu_ld32u, { "r", "L" } },
>> - =A0 =A0{ INDEX_op_qemu_ld32s, { "r", "L" } },
>>
>
> No. As I wrote in the original thread,
> conditional compilation is needed here
> (or you will get new compile errors).

In tcg/ppc/, TCG_TARGET_REG_BITS is always 32, isn't it?

Thanks,
Jay.