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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c383b45sm158194475e9.9.2025.11.03.05.14.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Nov 2025 05:14:53 -0800 (PST) Message-ID: Date: Mon, 3 Nov 2025 14:14:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 19/23] Workaround for ERRATA_772415_SPR17 Content-Language: en-US To: Zhenzhong Duan , qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com References: <20251024084349.102322-1-zhenzhong.duan@intel.com> <20251024084349.102322-20-zhenzhong.duan@intel.com> From: Eric Auger In-Reply-To: <20251024084349.102322-20-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/24/25 10:43 AM, Zhenzhong Duan wrote: > On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 > is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readonly > range mapped on second stage page table could still be written. > > Reference from 4th Gen Intel Xeon Processor Scalable Family Specification > Update, Errata Details, SPR17. > https://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/eagle-stream/sapphire-rapids-specification-update/ > > Also copied the SPR17 details from above link: > "Problem: When remapping hardware is configured by system software in > scalable mode as Nested (PGTT=011b) and with PWSNP field Set in the > PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended > Access bit if enabled) in first-stage page-table entries even when > second-stage mappings indicate that corresponding first-stage page-table > is Read-Only. > > Implication: Due to this erratum, pages mapped as Read-only in second-stage > page-tables may be modified by remapping hardware Access/Dirty bit updates. > > Workaround: None identified. System software enabling nested translations > for a VM should ensure that there are no read-only pages in the > corresponding second-stage mappings." > > Signed-off-by: Zhenzhong Duan > --- > hw/vfio/iommufd.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c > index f9d0926274..f9da0e79cc 100644 > --- a/hw/vfio/iommufd.c > +++ b/hw/vfio/iommufd.c > @@ -15,6 +15,7 @@ > #include > #include > > +#include "hw/iommu.h" > #include "hw/vfio/vfio-device.h" > #include "qemu/error-report.h" > #include "trace.h" > @@ -351,6 +352,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev, > VFIOContainer *bcontainer = VFIO_IOMMU(container); > uint32_t type, flags = 0; > uint64_t hw_caps; > + VendorCaps caps; > VFIOIOASHwpt *hwpt; > uint32_t hwpt_id; > int ret; > @@ -396,7 +398,8 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev, > * instead. > */ > if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devid, > - &type, NULL, 0, &hw_caps, errp)) { > + &type, &caps, sizeof(caps), &hw_caps, > + errp)) { > return false; > } > > @@ -411,6 +414,11 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev, > */ > if (vfio_device_get_viommu_flags_want_nesting(vbasedev)) { > flags |= IOMMU_HWPT_ALLOC_NEST_PARENT; > + > + if (host_iommu_extract_quirks(type, &caps) & Given that call site, I would rather implement a new PCIIOMMUOps, no? Eric > + HOST_IOMMU_QUIRK_NESTING_PARENT_BYPASS_RO) { > + bcontainer->bypass_ro = true; > + } > } > > if (cpr_is_incoming()) {