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Thu, 07 Oct 2021 10:25:50 -0700 (PDT) Subject: Re: [PULL 00/26] riscv-to-apply queue To: Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org References: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> From: Richard Henderson Message-ID: Date: Thu, 7 Oct 2021 10:25:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.964, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/6/21 11:47 PM, Alistair Francis wrote: > From: Alistair Francis > > The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def: > > Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007 > > for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07: > > hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000) > > ---------------------------------------------------------------- > Third RISC-V PR for QEMU 6.2 > > - Add Zb[abcs] instruction support > - Remove RVB support > - Bug fix of setting mstatus_hs.[SD|FS] bits > - Mark some UART devices as 'input' > - QOMify PolarFire MMUART > - Fixes for sifive PDMA > - Mark shakti_c as not user creatable > > ---------------------------------------------------------------- > Alistair Francis (1): > hw/riscv: shakti_c: Mark as not user creatable > > Bin Meng (5): > hw/char: ibex_uart: Register device in 'input' category > hw/char: shakti_uart: Register device in 'input' category > hw/char: sifive_uart: Register device in 'input' category > hw/dma: sifive_pdma: Fix Control.claim bit detection > hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed > > Frank Chang (1): > target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() > > Philipp Tomsich (16): > target/riscv: Introduce temporary in gen_add_uw() > target/riscv: fix clzw implementation to operate on arg1 > target/riscv: clwz must ignore high bits (use shift-left & changed logic) > target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties > target/riscv: Reassign instructions to the Zba-extension > target/riscv: Remove the W-form instructions from Zbs > target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) > target/riscv: Reassign instructions to the Zbs-extension > target/riscv: Add instructions of the Zbc-extension > target/riscv: Reassign instructions to the Zbb-extension > target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci > target/riscv: Add a REQUIRE_32BIT macro > target/riscv: Add rev8 instruction, removing grev/grevi > target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh > target/riscv: Remove RVB (replaced by Zb[abcs]) > disas/riscv: Add Zb[abcs] instructions > > Philippe Mathieu-Daudé (3): > hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition > hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container > hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART > > include/hw/char/mchp_pfsoc_mmuart.h | 17 +- > target/riscv/cpu.h | 11 +- > target/riscv/helper.h | 6 +- > target/riscv/insn32.decode | 115 ++++----- > disas/riscv.c | 157 +++++++++++- > hw/char/ibex_uart.c | 1 + > hw/char/mchp_pfsoc_mmuart.c | 116 +++++++-- > hw/char/shakti_uart.c | 1 + > hw/char/sifive_uart.c | 1 + > hw/dma/sifive_pdma.c | 13 +- > hw/riscv/shakti_c.c | 7 + > target/riscv/bitmanip_helper.c | 65 +---- > target/riscv/cpu.c | 30 +-- > target/riscv/translate.c | 36 ++- > target/riscv/insn_trans/trans_rvb.c.inc | 419 ++++++++++---------------------- > 15 files changed, 516 insertions(+), 479 deletions(-) Applied, thanks. Remember to update the wiki for the user-facing changes. r~