From: Richard Henderson <richard.henderson@linaro.org>
To: Yifei Jiang <jiangyifei@huawei.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com,
Alistair.Francis@wdc.com, yinyipeng1@huawei.com,
palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com
Subject: Re: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address
Date: Wed, 14 Oct 2020 13:21:46 -0700 [thread overview]
Message-ID: <ee4b99ec-5842-6638-ecff-54096ec0b0e8@linaro.org> (raw)
In-Reply-To: <20201014101728.848-1-jiangyifei@huawei.com>
On 10/14/20 3:17 AM, Yifei Jiang wrote:
> + if (fault_pte_addr) {
> + *fault_pte_addr = (base + idx * ptesize) >> 2;
The shift is wrong. It should be exactly like...
> + }
> + return TRANSLATE_G_STAGE_FAIL;
> }
>
> pte_addr = vbase + idx * ptesize;
... this.
r~
next prev parent reply other threads:[~2020-10-14 20:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-14 10:17 [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address Yifei Jiang
2020-10-14 20:06 ` Alistair Francis
2020-10-14 20:21 ` Richard Henderson [this message]
2020-10-15 1:59 ` Jiangyifei
2020-10-21 19:59 ` Alistair Francis
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