From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gWMwG-00065R-J1 for qemu-devel@nongnu.org; Mon, 10 Dec 2018 09:53:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gWMwC-0002MP-8u for qemu-devel@nongnu.org; Mon, 10 Dec 2018 09:53:40 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:38067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gWMwC-0002Ld-1a for qemu-devel@nongnu.org; Mon, 10 Dec 2018 09:53:36 -0500 Received: by mail-ot1-x342.google.com with SMTP id e12so10623634otl.5 for ; Mon, 10 Dec 2018 06:53:35 -0800 (PST) References: <20181206175541.29508-1-richard.henderson@linaro.org> <20181206175541.29508-2-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 10 Dec 2018 08:53:31 -0600 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 1/3] target/arm: Introduce arm_hcr_el2_eff List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 12/10/18 8:22 AM, Peter Maydell wrote: > This section that clears VI/VF/VSE is new, and I'm not sure it's right. > The spec says that the virtual IRQ interrupt is enabled only if {TGE,IMO} > is {0,1}, but the meaning of the bit is "pending", and an interrupt > can be pending without being enabled. Ditto VF, VSE. Fair enough. I can re-send with this section removed. r~