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References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de>
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 13 Oct 2018 12:54:40 -0700
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Subject: Re: [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm()
 decoding into trans_* functions
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org

On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
>  static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn)
>  {
> -    gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +    gen_get_gpr(source1, a->rs1);
> +
> +    tcg_gen_shli_tl(source1, source1, a->shamt);
> +    tcg_gen_ext32s_tl(source1, source1);
> +    gen_set_gpr(a->rd, source1);
> +
> +    tcg_temp_free(source1);
>      return true;
>  }

Now missing the TARGET_RISCV64 check.

> +static bool trans_arith_imm(DisasContext *ctx, arg_arith_imm *a,
> +                            void(*func)(TCGv, TCGv, TCGv))

gen_arith_imm.


r~