From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d651o-0001NH-Dl for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d651n-0005y6-GS for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:56 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1d651n-0005xn-AV for qemu-devel@nongnu.org; Wed, 03 May 2017 20:53:55 -0400 Received: by mail-pf0-x242.google.com with SMTP id o68so716375pfj.2 for ; Wed, 03 May 2017 17:53:55 -0700 (PDT) From: Stafford Horne Date: Thu, 4 May 2017 09:53:20 +0900 Message-Id: In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Development Cc: Stefan Hajnoczi , Stafford Horne These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 6ba8162..e13666b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; -- 2.9.3