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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id bk2sm3817982ejb.98.2021.02.11.02.21.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Feb 2021 02:21:46 -0800 (PST) Subject: Re: [PATCH v2 16/21] accel/tcg: actually cache our partial icount TB To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20210210221053.18050-1-alex.bennee@linaro.org> <20210210221053.18050-17-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 11 Feb 2021 11:21:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210210221053.18050-17-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.211, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , robhenry@microsoft.com, mahmoudabdalghany@outlook.com, aaron@os.amperecomputing.com, cota@braap.org, kuhn.chenqun@huawei.com, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Alex, On 2/10/21 11:10 PM, Alex Bennée wrote: > When we exit a block under icount with instructions left to execute we > might need a shorter than normal block to take us to the next > deterministic event. Instead of creating a throwaway block on demand > we use the existing compile flags mechanism to ensure we fetch (or > compile and fetch) a block with exactly the number of instructions we > need. > > Signed-off-by: Alex Bennée > Message-Id: <20210209182749.31323-8-alex.bennee@linaro.org> > > --- > v2 > - drop pointless assert > --- > accel/tcg/cpu-exec.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index d9ef69121c..5b6a4fe84b 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -730,16 +730,17 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, > /* Ensure global icount has gone forward */ > icount_update(cpu); > /* Refill decrementer and continue execution. */ > - insns_left = MIN(0xffff, cpu->icount_budget); > + insns_left = MIN(CF_COUNT_MASK, cpu->icount_budget); Can you describe this change a bit please? > cpu_neg(cpu)->icount_decr.u16.low = insns_left; > cpu->icount_extra = cpu->icount_budget - insns_left; > - if (!cpu->icount_extra && insns_left < tb->icount) { > - /* Execute any remaining instructions, then let the main loop > - * handle the next event. > - */ > - if (insns_left > 0) { > - cpu_exec_nocache(cpu, insns_left, tb, false); > - } > + > + /* > + * If the next tb has more instructions than we have left to > + * execute we need to ensure we find/generate a TB with exactly > + * insns_left instructions in it. > + */ > + if (!cpu->icount_extra && insns_left > 0 && insns_left < tb->icount) { > + cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; > } > #endif > } >