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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fd9ec84sm155817855e9.26.2025.03.25.11.47.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Mar 2025 11:47:34 -0700 (PDT) Message-ID: Date: Tue, 25 Mar 2025 19:47:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 12/20] hw/arm/smmuv3-accel: Return sysmem if stage-1 is bypassed Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-13-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250311141045.66620-13-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/11/25 3:10 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > When nested translation is enabled, there are 2-stage translation > occuring to two different address spaces: stage-1 in the iommu as, > while stage-2 in the system as. > > If a device attached to the vSMMU doesn't enable stage-1 translation, > e.g. vSTE sets to Config=Bypass, the system as should be returned, > so QEMU can set up system memory mappings onto the stage-2 page table. > This is crucial for an iommufd enabled VFIO device as the VFIO core > code would register an iommu notifier and replay the address space > which should be bypassed for this nested translation case. I would suggest to get inspired of 90519b90539 ("virtio-iommu: Add bypass mode support to assigned device") or similar patch on vtd (558e0024a428 intel_iommu: allow dynamic switch of IOMMU region + 4b519ef1de9a  intel-iommu: optimize nodmar memory regions), ie. use the same terminology and techniques/objects (switch_address_space) . To me this is not related to HW acceleration but rather to VFIO in general. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 22 +++++++++++++++++++++- > include/hw/arm/smmuv3-accel.h | 3 +++ > 2 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 056bd23b2e..76134d106a 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -18,6 +18,7 @@ > static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *sbus, > PCIBus *bus, int devfn) > { > + SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(s); > SMMUDevice *sdev = sbus->pbdev[devfn]; > SMMUv3AccelDevice *accel_dev; > > @@ -29,6 +30,8 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *sbus, > > sbus->pbdev[devfn] = sdev; > smmu_init_sdev(s, sdev, bus, devfn); > + address_space_init(&accel_dev->as_sysmem, &s_accel->root, > + "smmuv3-accel-sysmem"); > } > > return accel_dev; > @@ -351,12 +354,23 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, > SMMUPciBus *sbus; > SMMUv3AccelDevice *accel_dev; > SMMUDevice *sdev; > + PCIDevice *pdev = pci_find_device(bus, pci_bus_num(bus), devfn); > + bool has_iommufd = false; > + > + if (pdev) { > + has_iommufd = object_property_find(OBJECT(pdev), "iommufd"); > + } Refering to the discussion we had on how to set MSI RESV regions at virt-acpi-build level depending on whether the SMMU was accelerated I think we can use exactly the above method (checking accel property) > > sbus = smmu_get_sbus(s, bus); > accel_dev = smmuv3_accel_get_dev(s, sbus, bus, devfn); > sdev = &accel_dev->sdev; > > - return &sdev->as; > + /* Return the system as if the device uses stage-2 only */ > + if (has_iommufd && !accel_dev->s1_hwpt) { > + return &accel_dev->as_sysmem; > + } else { > + return &sdev->as; > + } > } > > static int smmuv3_accel_pxb_pcie_bus(Object *obj, void *opaque) > @@ -390,6 +404,12 @@ static void smmu_accel_realize(DeviceState *d, Error **errp) > error_propagate(errp, local_err); > return; > } > + > + memory_region_init(&s_accel->root, OBJECT(s_accel), "root", UINT64_MAX); > + memory_region_init_alias(&s_accel->sysmem, OBJECT(s_accel), > + "smmuv3-accel-sysmem", get_system_memory(), 0, > + memory_region_size(get_system_memory())); > + memory_region_add_subregion(&s_accel->root, 0, &s_accel->sysmem); > bs->get_address_space = smmuv3_accel_find_add_as; > bs->set_iommu_device = smmuv3_accel_set_iommu_device; > bs->unset_iommu_device = smmuv3_accel_unset_iommu_device; > diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h > index 54b217ab4f..58e68534c0 100644 > --- a/include/hw/arm/smmuv3-accel.h > +++ b/include/hw/arm/smmuv3-accel.h > @@ -51,12 +51,15 @@ typedef struct SMMUv3AccelDevice { > SMMUS1Hwpt *s1_hwpt; > SMMUViommu *viommu; > SMMUVdev *vdev; > + AddressSpace as_sysmem; > QLIST_ENTRY(SMMUv3AccelDevice) next; > } SMMUv3AccelDevice; > > struct SMMUv3AccelState { > SMMUv3State smmuv3_state; > SMMUViommu *viommu; > + MemoryRegion root; > + MemoryRegion sysmem; > }; > > struct SMMUv3AccelClass {