From: weiwei <liweiwei@iscas.ac.cn>
To: Bin Meng <bmeng@tinylab.org>, qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
Date: Tue, 14 Feb 2023 16:56:27 +0800 [thread overview]
Message-ID: <ef991710-bd3c-465b-0215-c0a1af350a59@iscas.ac.cn> (raw)
In-Reply-To: <20230213180215.1524938-10-bmeng@tinylab.org>
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On 2023/2/14 02:02, Bin Meng wrote:
> At present the odd-numbered PMP configuration registers for RV64 are
> reported in the CSR XML by QEMU gdbstub. However these registers do
> not exist on RV64 so trying to access them from gdb results in 'E14'.
>
> Move the pmpcfgX index check from the actual read/write routine to
> the PMP CSR predicate() routine, so that non-existent pmpcfgX won't
> be reported in the CSR XML for RV64.
>
> Signed-off-by: Bin Meng<bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
> ---
>
> target/riscv/csr.c | 23 ++++++++---------------
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0a3f2bef6f..749d0ef83e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -412,6 +412,14 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
> static RISCVException pmp(CPURISCVState *env, int csrno)
> {
> if (riscv_feature(env, RISCV_FEATURE_PMP)) {
> + if (csrno <= CSR_PMPCFG3) {
> + uint32_t reg_index = csrno - CSR_PMPCFG0;
> +
> + if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + }
> +
> return RISCV_EXCP_NONE;
> }
>
> @@ -3334,23 +3342,11 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
> -{
> - /* TODO: RV128 restriction check */
> - if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
> - return false;
> - }
> - return true;
> -}
> -
> static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> uint32_t reg_index = csrno - CSR_PMPCFG0;
>
> - if (!check_pmp_reg_index(env, reg_index)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> *val = pmpcfg_csr_read(env, reg_index);
> return RISCV_EXCP_NONE;
> }
> @@ -3360,9 +3356,6 @@ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
> {
> uint32_t reg_index = csrno - CSR_PMPCFG0;
>
> - if (!check_pmp_reg_index(env, reg_index)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> pmpcfg_csr_write(env, reg_index, val);
> return RISCV_EXCP_NONE;
> }
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next prev parent reply other threads:[~2023-02-14 8:57 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 18:01 [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-13 18:01 ` [PATCH 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-14 8:40 ` weiwei
2023-02-17 2:11 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check() Bin Meng
2023-02-14 8:43 ` weiwei
2023-02-17 2:15 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 03/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-14 8:45 ` weiwei
2023-02-17 2:20 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-02-14 8:46 ` weiwei
2023-02-17 2:23 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 05/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 06/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-14 8:50 ` [PATCH 07/18] target/riscv: Simplify {read,write}_pmpcfg() " weiwei
2023-02-17 2:26 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-14 8:51 ` weiwei
2023-02-17 2:30 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-14 8:56 ` weiwei [this message]
2023-02-17 2:36 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-14 9:02 ` weiwei
2023-02-17 2:39 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-14 9:13 ` weiwei
2023-02-17 2:43 ` LIU Zhiwei
2023-02-13 19:19 ` [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Daniel Henrique Barboza
2023-02-14 14:31 ` Bin Meng
2023-02-14 1:09 ` [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-14 9:16 ` weiwei
2023-02-17 2:48 ` LIU Zhiwei
2023-02-14 1:09 ` [PATCH 13/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-14 9:18 ` weiwei
2023-02-17 2:59 ` LIU Zhiwei
2023-02-14 3:06 ` [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-02-14 9:24 ` weiwei
2023-02-14 4:12 ` [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:12 ` [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:31 ` [PATCH 17/18] target/riscv: Group all predicate() routines together Bin Meng
2023-02-14 9:27 ` weiwei
2023-02-14 14:27 ` [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate() Bin Meng
2023-02-14 14:59 ` weiwei
2023-02-15 2:22 ` Bin Meng
2023-02-15 2:57 ` weiwei
2023-02-16 16:40 ` Palmer Dabbelt
2023-02-17 1:59 ` Bin Meng
2023-02-17 17:28 ` Palmer Dabbelt
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