From: Richard Henderson <richard.henderson@linaro.org>
To: Aleksandar Markovic <aleksandar.m.mail@gmail.com>,
Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Cc: Stefan Markovic <smarkovic@wavecomp.com>,
qemu-devel@nongnu.org,
Aleksandar Markovic <amarkovic@wavecomp.com>,
"Janeczek, Craig" <jancraig@amazon.com>
Subject: Re: [Qemu-devel] [PATCH 5/6] target/mips: MXU: Add handlers for max/min instructions
Date: Wed, 26 Dec 2018 06:34:48 +1100 [thread overview]
Message-ID: <eface3ff-cafd-da6f-3f6d-30496f168cd9@linaro.org> (raw)
In-Reply-To: <CAL1e-=gUE7KPL+MwBOd_sb2KocHox-4Davo_SN2fwozBoOa20Q@mail.gmail.com>
Sorry I missed the original post, but:
> + } else if (unlikely((XRb == 0) && (XRc == 0))) {
> + /* both operands zero registers -> just set destination to zero */
> + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> + } else if (unlikely((XRb == 0) || (XRc == 0))) {
> + /* exactly one operand is zero register - find which one is not...*/
> + uint32_t XRx = XRb ? XRb : XRc;
> + /* ...and do max/min operation with one operand 0 */
> + if (opc == OPC_MXU_S32MAX) {
> + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
> + } else {
> + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
> + }
> + } else if (unlikely(XRb == XRc)) {
> + /* both operands same -> just set destination to one of them */
> + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
You should not special case unlikely events, especially when ...
> + } else {
> + /* the most general case */
> + if (opc == OPC_MXU_S32MAX) {
> + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
> + mxu_gpr[XRc - 1]);
> + } else {
> + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
> + mxu_gpr[XRc - 1]);
> + }
... the normal case will handle those special cases just fine.
next prev parent reply other threads:[~2018-12-25 19:35 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-17 20:04 [Qemu-devel] [PATCH 0/6] target/mips: Amend MXU support Aleksandar Markovic
2018-12-17 20:04 ` [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions Aleksandar Markovic
2018-12-18 14:21 ` Stefan Markovic
2018-12-27 17:15 ` Janeczek, Craig
2018-12-27 18:44 ` Aleksandar Markovic
2018-12-27 18:50 ` Janeczek, Craig
2018-12-27 19:23 ` Aleksandar Markovic
2018-12-27 19:37 ` Janeczek, Craig
2018-12-27 20:12 ` Aleksandar Markovic
2018-12-17 20:04 ` [Qemu-devel] [PATCH 2/6] target/mips: MXU: Add generic naming for optn2 constants Aleksandar Markovic
2018-12-17 20:04 ` [Qemu-devel] [PATCH 3/6] target/mips: MXU: Improve textual description Aleksandar Markovic
2018-12-18 14:30 ` Stefan Markovic
2018-12-17 20:04 ` [Qemu-devel] [PATCH 4/6] target/mips: MXU: Add handlers for logic instructions Aleksandar Markovic
2018-12-18 14:39 ` Stefan Markovic
2018-12-17 20:04 ` [Qemu-devel] [PATCH 5/6] target/mips: MXU: Add handlers for max/min instructions Aleksandar Markovic
2018-12-18 15:05 ` Stefan Markovic
2018-12-27 17:18 ` Janeczek, Craig
2018-12-27 20:14 ` Aleksandar Markovic
2018-12-23 17:22 ` Aleksandar Markovic
2018-12-25 19:34 ` Richard Henderson [this message]
2021-03-15 21:26 ` Philippe Mathieu-Daudé
2018-12-17 20:04 ` [Qemu-devel] [PATCH 6/6] target/mips: MXU: Add handlers for an align instruction Aleksandar Markovic
2018-12-18 15:19 ` Stefan Markovic
2018-12-27 21:27 ` [Qemu-devel] [PATCH 0/6] target/mips: Amend MXU support Aleksandar Markovic
2018-12-31 14:40 ` Aleksandar Markovic
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