Re: [Qemu-devel] [PATCH v2 09/11] target/ppc: add ov32 flag for multiply low insns

[Richard Henderson <rth@twiddle.net>]

On 02/22/2017 08:29 PM, Nikunj A Dadhania wrote:
> For Multiply Word:
> SO, OV, and OV32 bits reflects overflow of the 32-bit result
>
> For Multiply DoubleWord:
> SO, OV, and OV32 bits reflects overflow of the 64-bit result
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
> ---
>  target/ppc/translate.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2a9f508..d676863 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1288,6 +1288,7 @@ static void gen_mullwo(DisasContext *ctx)
>      tcg_gen_sari_i32(t0, t0, 31);
>      tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
>      tcg_gen_extu_i32_tl(cpu_ov, t0);
> +    tcg_gen_mov_tl(cpu_ov32, cpu_ov);
>      tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
>
>      tcg_temp_free_i32(t0);
> @@ -1349,6 +1350,7 @@ static void gen_mulldo(DisasContext *ctx)
>
>      tcg_gen_sari_i64(t0, t0, 63);
>      tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
> +    tcg_gen_mov_tl(cpu_ov32, cpu_ov);
>      tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);

isa300 checks?


r~