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[83.59.163.107]) by smtp.gmail.com with ESMTPSA id cb21sm946521edb.57.2021.02.03.06.27.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Feb 2021 06:27:36 -0800 (PST) Subject: Re: [PATCH v15 18/23] accel: introduce AccelCPUClass extending CPUClass To: Claudio Fontana , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Peter Maydell References: <20210201100903.17309-1-cfontana@suse.de> <20210201100903.17309-19-cfontana@suse.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 3 Feb 2021 15:27:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210201100903.17309-19-cfontana@suse.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.539, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.178, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Alistair Francis , Roman Bolshakov , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/1/21 11:08 AM, Claudio Fontana wrote: > add a new optional interface to CPUClass, which allows accelerators > to extend the CPUClass with additional accelerator-specific > initializations. > > Signed-off-by: Claudio Fontana > --- > include/hw/core/accel-cpu.h | 35 +++++++++++++++++++++++++++++ > include/hw/core/cpu.h | 1 + > accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++ > MAINTAINERS | 1 + > 4 files changed, 81 insertions(+) > create mode 100644 include/hw/core/accel-cpu.h > > diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h > new file mode 100644 > index 0000000000..c7c137dc9a > --- /dev/null > +++ b/include/hw/core/accel-cpu.h > @@ -0,0 +1,35 @@ > +/* > + * Accelerator interface, specializes CPUClass > + * > + * Copyright 2021 SUSE LLC > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + */ > + > +#ifndef ACCEL_CPU_H > +#define ACCEL_CPU_H > + > +/* > + * these defines cannot be in cpu.h, because we are using > + * CPU_RESOLVING_TYPE here. > + * Use this header to define your accelerator-specific > + * cpu-specific accelerator interfaces. > + */ > + > +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE > +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) > +typedef struct AccelCPUClass AccelCPUClass; > +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) > + > +typedef struct AccelCPUClass { > + /*< private >*/ > + ObjectClass parent_class; > + /*< public >*/ > + > + void (*cpu_class_init)(CPUClass *cc); > + void (*cpu_instance_init)(CPUState *cpu); > + void (*cpu_realizefn)(CPUState *cpu, Error **errp); > +} AccelCPUClass; This header only makes sense if you forward-declare CPUClass in "qemu/typedefs.h", so accelerators don't have to include "hw/core/cpu.h".