Re: [PATCH v6 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer

[Harsh Prateek Bora <harshpb@linux.ibm.com>]

On 9/26/25 01:47, Glenn Miles wrote:
> The IBM PPE42 processors support a 32-bit decrementer
> that can raise an external interrupt when DEC[0]
> transitions from a 0 to a 1 (a non-negative value to a

I guess it was meant to be 0 to -1 (0xffffffff)?
No need to re-spin just for that though.

> negative value).  It also continues decrementing
> even after this condition is met.
> 
> The BookE timer is slightly different in that it
> raises an interrupt when the DEC value reaches 0
> and stops decrementing at that point.
> 
> Support a PPE42 version of the BookE timer by
> adding a new PPC_TIMER_PPE flag that has the timer
> code look for the transition from a non-negative value
> to a negative value and allows the value to
> continue decrementing.
> 
> Signed-off-by: Glenn Miles <milesg@linux.ibm.com>

Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>

> ---
>   hw/ppc/ppc_booke.c   | 7 ++++++-
>   include/hw/ppc/ppc.h | 1 +
>   2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
> index 3872ae2822..13403a56b1 100644
> --- a/hw/ppc/ppc_booke.c
> +++ b/hw/ppc/ppc_booke.c
> @@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
>       booke_timer = g_new0(booke_timer_t, 1);
>   
>       cpu->env.tb_env = tb_env;
> -    tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
> +    if (flags & PPC_TIMER_PPE) {
> +        /* PPE's use a modified version of the booke behavior */
> +        tb_env->flags = flags | PPC_DECR_UNDERFLOW_TRIGGERED;
> +    } else {
> +        tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
> +    }
>   
>       tb_env->tb_freq    = freq;
>       tb_env->decr_freq  = freq;
> diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
> index 8a14d623f8..cb51d704c6 100644
> --- a/include/hw/ppc/ppc.h
> +++ b/include/hw/ppc/ppc.h
> @@ -52,6 +52,7 @@ struct ppc_tb_t {
>   #define PPC_DECR_UNDERFLOW_LEVEL     (1 << 4) /* Decr interrupt active when
>                                                  * the most significant bit is 1.
>                                                  */
> +#define PPC_TIMER_PPE                (1 << 5) /* Enable PPE support */
>   
>   uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
>   void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq);