From: Richard Henderson <richard.henderson@linaro.org>
To: Laurent Vivier <laurent@vivier.eu>, qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] target/m68k: Clear mach in m68k_cpu_disas_set_info
Date: Tue, 17 May 2022 09:06:21 -0700 [thread overview]
Message-ID: <f0318317-5a50-26d7-0365-6ed48dd070d1@linaro.org> (raw)
In-Reply-To: <4fd55674-87ae-5e19-f43b-04ba102e4300@vivier.eu>
On 5/17/22 07:06, Laurent Vivier wrote:
> Le 30/04/2022 à 19:02, Richard Henderson a écrit :
>> Zero selects all cpu features in disas/m68k.c,
>> which is really what we want -- not limited to 68040.
>
> But what happens when an instruction has to be decoded differently between 680x0 and
> coldfire?
>
> for instance in disas/m68k.c, we have:
>
> {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
> {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
>
> {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
> {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
>
> {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
> {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
>
> {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
> {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
>
> {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
> {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
>
> {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
> {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
>
> {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
> {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
> {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
> {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
>
> {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
> {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
>
> {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
> {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
> {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
> {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
> {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
> {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
They're all compatible encodings, it's just that the CF ones are more restricted. When
debugging a SIGILL on CF, it would be nicer to see
addl a0@, d0
than
.byte xx, yy
in the -d in_asm dump.
r~
next prev parent reply other threads:[~2022-05-17 16:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-30 17:02 [PATCH 0/2] target/m68k: Enable halt insn for 68060 Richard Henderson
2022-04-30 17:02 ` [PATCH 1/2] target/m68k: Clear mach in m68k_cpu_disas_set_info Richard Henderson
2022-05-17 14:06 ` Laurent Vivier
2022-05-17 16:06 ` Richard Henderson [this message]
2022-05-18 21:57 ` Laurent Vivier
2022-04-30 17:02 ` [PATCH 2/2] target/m68k: Enable halt insn for 68060 Richard Henderson
2022-05-17 14:09 ` Laurent Vivier
2022-05-26 17:08 ` [PATCH 0/2] " Laurent Vivier
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