From: Paolo Bonzini <pbonzini@redhat.com>
To: Michael Clark <mjc@sifive.com>, Peter Maydell <peter.maydell@linaro.org>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2
Date: Thu, 8 Mar 2018 12:49:01 +0100 [thread overview]
Message-ID: <f03bbee3-f308-9ec8-050e-3a0534837b9c@redhat.com> (raw)
In-Reply-To: <CAHNT7NuqgY-zgPJT4gUJMaHr24E-PwrN=Eje+m1XW24mAf07Ag@mail.gmail.com>
On 08/03/2018 12:18, Michael Clark wrote:
>> There are multiple sign-offs in all
>> 23 commits. The tag is riscv-qemu-upstream-v8.2
Except your cover letter lists 45 commits and, as Daniel has already confirmed,
Peter is right: these commits listed in the cover letter have no sign-off and
have not been reviewed:
RISC-V - Make virt create_fdt interface consistent with other boards
RISC-V - Replace hardcoded device-tree constants with enum values
RISC-V - Make virt board description match spike format
RISC-V - Use ROM base address and size constants from memory map
RISC-V - Remove redundant identity_translate callback from load_elf
RISC-V - Mark ROM read-only after copying in reset vector and config
RISC-V - Remove unused class definitions from machines
RISC-V - Make sure the emulated mask rom has space for device-tree
RISC-V - Include hexidecimal instruction packets in disassembly
RISC-V - Need to hold rcu_read_lock when accessing memory directly
RISC-V - Improve page table walker spec compliance and add comments
RISC-V - Update E order and note that add E and I are mutually exclusive
RISC-V - Make spike and virt header guards more specific
RISC-V - Make virt header comment consistent with source file
RISC-V - Use memory_region_is_ram in atomic pte update
RISC-V - Remove EM_RISCV ELF_MACHINE indirection from load_elf
RISC-V - Ingore satp writes and return 0 for reads when no-mmu
RISC-V - Remove braces from satp case statement with no locals
RISC-V - riscv-qemu port supports sv39 and sv48
RISC-V - vectored traps for asynchrounous interrupts are optional
RISC-V - Dont' trap on writes to misa,minstret[h],mcycle[h]
RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
>
> I have complied with practically every review request and the sign-offs are
> there. It’s a bit ridiculous.
>
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
Just don't do this. If you don't trust the maintainers, I don't see why
the maintainers should merge the RISC-V port; no one needs an history
lesson on RISC or ARM or RISC-V either. And you can understand that adding
and reviewing 10K lines of code requires a significant effort, that some of
the maintainers are doing in their spare time.
In fact, I looked at "RISC-V - Need to hold rcu_read_lock when accessing
memory directly" and from a first look it's wrong. So I think you owe an
apology...
Paolo
next prev parent reply other threads:[~2018-03-08 11:49 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-06 19:46 [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2 Michael Clark
2018-03-07 0:09 ` Michael Clark
2018-03-07 10:11 ` Richard W.M. Jones
2018-03-07 12:15 ` Michael Clark
2018-03-08 10:02 ` Peter Maydell
2018-03-08 11:10 ` Michael Clark
2018-03-08 11:18 ` Michael Clark
2018-03-08 11:41 ` Michael Clark
2018-03-08 11:52 ` Stefan Hajnoczi
2018-03-08 19:29 ` [Qemu-devel] [patches] " Palmer Dabbelt
2018-03-08 19:53 ` Michael Clark
2018-03-09 14:28 ` Peter Maydell
2018-03-09 14:51 ` Michael Clark
2018-03-09 15:15 ` Alex Bennée
2018-03-09 15:22 ` Peter Maydell
2018-03-09 16:49 ` Peter Maydell
2018-03-09 20:11 ` Michael Clark
2018-03-09 20:23 ` Michael Clark
2018-03-08 11:48 ` [Qemu-devel] " Daniel P. Berrangé
2018-03-08 20:03 ` Michael Clark
2018-03-08 11:49 ` Paolo Bonzini [this message]
2018-03-08 11:19 ` Peter Maydell
2018-03-08 11:36 ` Daniel P. Berrangé
2018-03-08 11:33 ` Daniel P. Berrangé
2018-03-08 11:42 ` Daniel P. Berrangé
2018-03-08 12:25 ` Daniel P. Berrangé
2018-03-08 12:39 ` Paolo Bonzini
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