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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf34491a7fsm27152781f8f.57.2025.09.04.07.33.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:33:26 -0700 (PDT) Message-ID: Date: Thu, 4 Sep 2025 16:33:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Content-Language: en-US To: Nicolin Chen , skolothumtho@nvidia.com Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, jgg@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, shameerkolothum@gmail.com References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> <20250714155941.22176-6-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/14/25 7:23 PM, Nicolin Chen wrote: > On Mon, Jul 14, 2025 at 04:59:31PM +0100, Shameer Kolothum wrote: >> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel >> SMMUv3 will have different handling for those ops callbacks >> in subsequent patches. >> >> The "accel" property is not yet added, so users cannot set it at this >> point. It will be introduced in a subsequent patch once the necessary >> support is in place. >> >> Signed-off-by: Shameer Kolothum > Overall the patch looks good to me, > Reviewed-by: Nicolin Chen > > with some nits: > >> @@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) >> arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) >> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c')) >> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c')) >> -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) >> +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) >> +arm_ss.add(when: ['CONFIG_ARM_SMMUV3', 'CONFIG_IOMMUFD'], if_true: files('smmuv3-accel.c')) > Wondering why "arm_common_ss" is changed to "arm_ss"? Indeed why did you need to change that? Thanks Eric > >> +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *sbus, >> + PCIBus *bus, int devfn) > There seems to be an extra space in the 2nd line. > >> +{ >> + SMMUDevice *sdev = sbus->pbdev[devfn]; >> + SMMUv3AccelDevice *accel_dev; >> + >> + if (sdev) { >> + accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev); >> + } else { >> + accel_dev = g_new0(SMMUv3AccelDevice, 1); >> + sdev = &accel_dev->sdev; >> + >> + sbus->pbdev[devfn] = sdev; >> + smmu_init_sdev(bs, sdev, bus, devfn); >> + } > Could just: > if (sdev) { > return container_of(sdev, SMMUv3AccelDevice, sdev); > } > > Then, no extra indentations for the rest of the code. > >> + >> + return accel_dev; >> +} >> + >> +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, >> + int devfn) >> +{ >> + SMMUState *bs = opaque; >> + SMMUPciBus *sbus; >> + SMMUv3AccelDevice *accel_dev; >> + SMMUDevice *sdev; >> + >> + sbus = smmu_get_sbus(bs, bus); >> + accel_dev = smmuv3_accel_get_dev(bs, sbus, bus, devfn); >> + sdev = &accel_dev->sdev; > Maybe just: > > + SMMUPciBus *sbus = smmu_get_sbus(bs, bus); > + SMMUv3AccelDevice *accel_dev = smmuv3_accel_get_dev(bs, sbus, bus, devfn); > + SMMUDevice *sdev = &accel_dev->sdev; > > ? > >> +typedef struct SMMUv3AccelDevice { >> + SMMUDevice sdev; > Let's drop the extra space in between. > >> +} SMMUv3AccelDevice; >> + >> +#endif /* HW_ARM_SMMUV3_ACCEL_H */ >> diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h >> index eb94623555..c459d24427 100644 >> --- a/include/hw/arm/smmu-common.h >> +++ b/include/hw/arm/smmu-common.h >> @@ -162,6 +162,7 @@ struct SMMUState { >> uint8_t bus_num; >> PCIBus *primary_bus; >> bool smmu_per_bus; /* SMMU is specific to the primary_bus */ >> + bool accel; /* SMMU has accelerator support */ > How about: > "SMMU is in the HW-accelerated mode for stage-1 translation" > ? > > Thanks > Nicolin >