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Mon, 31 Jul 2023 08:26:02 +0000 (GMT) Message-ID: Subject: Re: [PATCH] target/s390x: Move trans_exc_code update to do_program_interrupt From: Ilya Leoshkevich To: Richard Henderson , qemu-devel@nongnu.org Cc: david@redhat.com, qemu-s390x@nongnu.org, Claudio Fontana Date: Mon, 31 Jul 2023 10:26:01 +0200 In-Reply-To: <920b0af5-4acb-3eaa-755f-608359117cd2@linaro.org> References: <20230728195538.488932-1-richard.henderson@linaro.org> <920b0af5-4acb-3eaa-755f-608359117cd2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: x2A-lH9cChAVQjx1ooLnrJLOUPn6tb5f X-Proofpoint-ORIG-GUID: 3TpxQRmqNYcP7JO5XfpJ3Erc0dbMPwVW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-31_01,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 priorityscore=1501 adultscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307310072 Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, 2023-07-28 at 13:02 -0700, Richard Henderson wrote: > On 7/28/23 12:55, Richard Henderson wrote: > > This solves a problem in which the store to LowCore during tlb_fill > > triggers a clean-page TB invalidation for page0 during translation, > > which results in an assertion failure for locked pages. > >=20 > > By delaying the store until after the exception has been raised, > > we will have unwound the pages locked for translation and the > > problem does not arise.=C2=A0 There are plenty of other updates to > > LowCore while delivering an interrupt/exception; trans_exc_code > > does not need to be special. > >=20 > > Reported-by: Claudio Fontana > > Signed-off-by: Richard Henderson > > --- > > =C2=A0 target/s390x/tcg/excp_helper.c | 42 +++++++++++++++++++++++-----= - > > ----- > > =C2=A0 1 file changed, 29 insertions(+), 13 deletions(-) [...] > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 switch (env->int_pgm_code) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case PGM_PER: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (env->per_perc_atmid & P= ER_CODE_EVENT_NULLIFICATION) { > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bre= ak; > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* FALL THROUGH */ > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 advance =3D !(env->per_perc= _atmid & > > PER_CODE_EVENT_NULLIFICATION); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; > > +=C2=A0=C2=A0=C2=A0 case PGM_ASCE_TYPE: > > +=C2=A0=C2=A0=C2=A0 case PGM_REG_FIRST_TRANS: > > +=C2=A0=C2=A0=C2=A0 case PGM_REG_SEC_TRANS: > > +=C2=A0=C2=A0=C2=A0 case PGM_REG_THIRD_TRANS: > > +=C2=A0=C2=A0=C2=A0 case PGM_SEGMENT_TRANS: > > +=C2=A0=C2=A0=C2=A0 case PGM_PAGE_TRANS: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 assert(env->int_pgm_code = =3D=3D env->tlb_fill_exc); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 set_trans_exc_code =3D true= ; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >=20 > I should have mentioned that this block of exceptions came from page > 3-76=20 > (Translation-Exception Identification for DAT Exceptions) of the 13th > edition of the PoO. >=20 > > +=C2=A0=C2=A0=C2=A0 case PGM_PROTECTION: > > +=C2=A0=C2=A0=C2=A0 case PGM_TRANS_SPEC: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 assert(env->int_pgm_code = =3D=3D env->tlb_fill_exc); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 set_trans_exc_code =3D true= ; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 advance =3D true; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >=20 > These exceptions came from seeing an early kernel fault, grepping for > the set of=20 > exceptions raised in mmu_helper.c, and eliminating PGM_ADDRESSING per > the first hunk. Does POp specify that the CPU stores Translation-Exception Identification on Translation-Specification Exceptions (PGM_TRANS_SPEC)? I re-read the 0xA8 documentation a few times, but could not find it. It's also interesting what the kernel was attempting when it got PGM_TRANS_SPEC and recovered from it. Maybe something else is wrong? Other than the POp question: Reviewed-by: Ilya Leoshkevich >=20 > I wasn't sure where to look for the full specification of exception > effects, but this did=20 > solve the kernel fault. >=20 >=20 > r~