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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id k9sm14510552pgq.27.2021.05.25.07.26.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 May 2021 07:26:07 -0700 (PDT) Subject: Re: [PATCHv2] target/arm: make pointer authentication a switchable feature To: Jamie Iles , qemu-arm@nongnu.org References: <20210525090104.1761645-1-jamie@nuviainc.com> From: Richard Henderson Message-ID: Date: Tue, 25 May 2021 07:26:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210525090104.1761645-1-jamie@nuviainc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , leif@nuviainc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/25/21 2:01 AM, Jamie Iles wrote: > Rather than having pointer authentication properties be specific to the > max CPU type, turn this into a generic feature that can be set for each > CPU model. This means that for future CPU types the feature can be set > without having the ID_AA64ISAR1 bits clobbered in > arm_cpu_pauth_finalize. This also makes it possible for real CPU models > to use the impdef algorithm for improved performance by setting > pauth-impdef=on on the command line. > > Cc: Richard Henderson > Cc: Peter Maydell > Signed-off-by: Jamie Iles > --- > > Following Richard's suggestion to make impdef selectable for all CPUs > where pointer auth is supported, I've moved this up to a full feature > and then any future CPUs supporting pointer auth can just set > ARM_FEATURE_PAUTH. New patches should not be in-reply-to another thread. They get lost that way. > bool prop_pauth; > bool prop_pauth_impdef; > + bool has_pauth; What's this for? It doesn't even seem to be used in this patch. > @@ -2115,6 +2116,7 @@ enum arm_features { > ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ > ARM_FEATURE_M_MAIN, /* M profile Main Extension */ > ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ > + ARM_FEATURE_PAUTH, /* has pointer authentication support */ > }; > > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index f42803ecaf1d..5a4386ce9218 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -760,10 +760,7 @@ static void aarch64_max_initfn(Object *obj) > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > #endif > - > - /* Default to PAUTH on, with the architected algorithm. */ > - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); > - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); > + set_feature(&cpu->env, ARM_FEATURE_PAUTH); I would rather you split out a function akin to aarch64_add_sve_properties, e.g. aarch64_add_pauth_properties. We would call this function in any cpufoo_initfn that enables pauth. It is hard to say more without the patch that adds the cpufoo_initfn which you are interested in. > + /* Default to PAUTH on, with the architected algorithm. */ > + if (arm_feature(&cpu->env, ARM_FEATURE_PAUTH)) { FWIW, this test is cpu_isar_feature(aa64_pauth, cpu) without having to add ARM_FEATURE_PAUTH. r~