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Thu, 15 May 2025 16:04:58 +0000 (GMT) Message-ID: Subject: Re: [PATCH 34/50] ppc/xive: tctx_accept only lower irq line if an interrupt was presented From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 11:04:58 -0500 In-Reply-To: <20250512031100.439842-35-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-35-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=Cf0I5Krl c=1 sm=1 tr=0 ts=682610ae cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=pRnG_qZzie8L9V9X0xMA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfXz8pxyDMHfdlO 1tSTKA7n9eTTImGy0c6TpoRwbGnIo6RzlS7E0d7DoiW8GHJ1Ga7cMGp0spGotn3+UHukRmr+JnC vftJcwonooaxrInbaEikef7tVT7SLn9T1fQme5YJ5rvboDPXAqEQy2P1b+DZv8/DNk/qgxVUdJG DLCNP9V62w1kyz1Acx4r+lRjJaBvAMYr6yhz5b+jz1OsxikF+4x5nDh9H+k1Vdn/j31dy9alo1s nGqY1t188YOZ3vyoM3JZ1DNWfMsi0VHSU4NoZeQ8uEF2BLoMX8HjrkOiAvPRJO+PSTyKWK7vIEU 3PVWNHd+tpXfnjh4Bq09TAM+pf5KHRhXuwfaPqcNbQla0jrKDo8SQvTEGwihFkq1o/j/Fz5j5fV uC7dCo1466uAAnjAjQ+d0Q4PvZ5xzFOpNtsgRrW0aufW5fvmrlwe1nlUaJ07oPF8rZ4TcgdR X-Proofpoint-GUID: eo9jRLMosPC5Z8qfOKUGE5_VR6NZwRlt X-Proofpoint-ORIG-GUID: YNHty2v-7OFa_h5zLTE68mAUbxYy92ru X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=891 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > The relationship between an interrupt signaled in the TIMA and the QEMU > irq line to the processor to be 1:1, so they should be raised and > lowered together and "just in case" lowering should be avoided (it could > mask > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 4e0c71d684..d5dbeab6bd 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) > g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); > g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); > > - qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); > - > if (xive_nsr_indicates_exception(sig_ring, nsr)) { > uint8_t cppr = sig_regs[TM_PIPR]; > uint8_t ring; > @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) > > /* Clear the exception from NSR */ > sig_regs[TM_NSR] = 0; > + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); > > trace_xive_tctx_accept(tctx->cs->cpu_index, ring, > regs[TM_IPB], sig_regs[TM_PIPR],