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Mon, 01 Sep 2025 21:06:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFa7d/f4qX/2jeO69pwcSuiF/kcxjVQeT+Ewj/vmwhjI3RyzEKX9KAvbXSSf6K+lg+7lTvhWA== X-Received: by 2002:a17:902:e552:b0:24a:f79e:e5eb with SMTP id d9443c01a7336-24af79eeaa3mr43405225ad.49.1756785991763; Mon, 01 Sep 2025 21:06:31 -0700 (PDT) Received: from [172.19.248.181] ([80.149.170.9]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24903727e23sm119538555ad.45.2025.09.01.21.06.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 21:06:31 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2025 20:39:18 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/39] target/hexagon: Implement modify SSR To: Richard Henderson , ltaylorsimpson@gmail.com, 'Sid Manning' , qemu-devel@nongnu.org Cc: philmd@linaro.org, "'Matheus Bernardino (QUIC)'" , ale@rev.ng, anjo@rev.ng, "'Marco Liebel (QUIC)'" , alex.bennee@linaro.org, "'Mark Burton (QUIC)'" , 'Brian Cain' References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-6-brian.cain@oss.qualcomm.com> <017101db9763$41ae4ca0$c50ae5e0$@gmail.com> <026201db9839$f4bb6040$de3220c0$@gmail.com> <2712e0cb-72a3-4c39-82a4-4b5f6d4914b0@oss.qualcomm.com> <02ae01db98ed$6d15add0$47410970$@gmail.com> <64531a80-822a-4d90-8731-0e632e7f8da7@linaro.org> Content-Language: en-US From: Brian Cain In-Reply-To: <64531a80-822a-4d90-8731-0e632e7f8da7@linaro.org> Content-Type: text/plain; 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envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/19/2025 11:58 AM, Richard Henderson wrote: > On 3/19/25 09:39, ltaylorsimpson@gmail.com wrote: >> I caution against putting a level of indirection into CPUHexagonState >> for the HVX registers.  The HVX TCG implementation relies on an >> offset from the start of CPUHexagonState to identify the operands.  >> This would be a very significant rewrite if it's even possible.  I >> don't know if TCG's gvec code generation can handle random pointers >> or a level of indirection. > > > Not yet, it can't, no. > > I've been extending it for random pointers because of Arm FEAT_SME2, > wherein we have indirect addressing of matrix slices. So we wind up > with a pointer like > >   &env->zarray + (env->xregs[reg] + offset) % size > > >> If the behavior is undefined, we can avoid the copies.  Then we just >> need some bookkeeping to check if multiple threads try to claim the >> same context (if that behavior is defined).  If copies are needed, we >> could keep the  hardware contexts as shared a shared resource.  >> Another alternative would be to track the current owner of a context >> and copy from the previous owner's {VQ}Regs to the new owners {VQ}Regs. > > Depending on how you answer these questions, I could split out the TCG > work. > But in the short term, copying context data might well be easier. > I've removed HVX context management from this series and will propose it in a future one.  Indeed the behavior is undefined when multiple hardware threads try to access the same context.  If the TCG changes for indirection show up at some point (or have already shown up) that would be great for us to take advantage of.  But the copies seem adequate for now. > > r~