From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: P J P <ppandit@redhat.com>, Peter Maydell <peter.maydell@linaro.org>
Cc: liqsub1 <liqsub1@163.com>,
Qemu Developers <qemu-devel@nongnu.org>,
Moguofang <moguofang@huawei.com>
Subject: Re: [Qemu-devel] [PATCH v2] strongarm: mask off high[32:28] bits from dir and state registers
Date: Tue, 30 Oct 2018 14:25:33 +0100 [thread overview]
Message-ID: <f15fc5de-43ff-0178-f4da-559b5008fdce@redhat.com> (raw)
In-Reply-To: <nycvar.YSQ.7.76.1810301716590.30516@xnncv>
On 30/10/18 12:49, P J P wrote:
> +-- On Mon, 29 Oct 2018, Peter Maydell wrote --+
> | > switch (offset) {
> | > case GPDR: /* GPIO Pin-Direction registers */
> | > - s->dir = value;
> | > + s->dir = value & 0x3fffff;
> |
> | The commit message says it's masking [31:28], but the
> | code is masking [31:22]. The SA1110 spec suggests the
> | commit message is correct and the code is not.
>
> Ouch, sorry! Sent revised patch v3.
That's where the extract32() is more convenient and less bug prone:
s->dir = extract32(value, 0, 28); /* mask off [31:28] */
>
> Thank you.
> --
> Prasad J Pandit / Red Hat Product Security Team
> 47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
>
prev parent reply other threads:[~2018-10-30 13:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-26 7:30 [Qemu-devel] [PATCH v2] strongarm: mask off high[32:28] bits from dir and state registers P J P
2018-10-29 13:14 ` Peter Maydell
2018-10-30 11:49 ` P J P
2018-10-30 13:25 ` Philippe Mathieu-Daudé [this message]
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