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Tue, 25 Apr 2023 22:31:55 -0700 (PDT) Received: from [10.72.12.241] ([43.228.180.230]) by smtp.gmail.com with ESMTPSA id jw16-20020a170903279000b0019cd1ee1523sm9155827plb.30.2023.04.25.22.31.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Apr 2023 22:31:55 -0700 (PDT) Message-ID: Date: Wed, 26 Apr 2023 13:31:45 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [RFC PATCH 1/4] pci: add handling of Enable bit in ATS Control Register Content-Language: en-US To: Viktor Prutyanov , mst@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, peterx@redhat.com, david@redhat.com Cc: philmd@linaro.org, qemu-devel@nongnu.org, yan@daynix.com, yuri.benditovich@daynix.com References: <20230424112147.17083-1-viktor@daynix.com> <20230424112147.17083-2-viktor@daynix.com> From: Jason Wang In-Reply-To: <20230424112147.17083-2-viktor@daynix.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -36 X-Spam_score: -3.7 X-Spam_bar: --- X-Spam_report: (-3.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.171, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.422, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 在 2023/4/24 19:21, Viktor Prutyanov 写道: > According to PCIe Address Translation Services specification 5.1.3., > ATS Control Register has Enable bit to enable/disable ATS. > Add a new field for a trigger function which is called at the Enable > bit change, so that PCIe devices can handle ATS enable/disable. > > Signed-off-by: Viktor Prutyanov > --- > hw/pci/pci.c | 1 + > hw/pci/pcie.c | 21 +++++++++++++++++++++ > include/hw/pci/pci_device.h | 3 +++ > include/hw/pci/pcie.h | 4 ++++ > 4 files changed, 29 insertions(+) > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > index 208c16f450..79a47d2589 100644 > --- a/hw/pci/pci.c > +++ b/hw/pci/pci.c > @@ -1550,6 +1550,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int > msi_write_config(d, addr, val_in, l); > msix_write_config(d, addr, val_in, l); > pcie_sriov_config_write(d, addr, val_in, l); > + pcie_ats_config_write(d, addr, val_in, l); > } > > /***********************************************************/ > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 924fdabd15..e0217161e5 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -1057,6 +1057,27 @@ void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned) > pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); > } > > +void pcie_ats_config_write(PCIDevice *dev, uint32_t address, uint32_t val, > + int len) > +{ > + uint32_t off; > + uint16_t ats_cap = dev->exp.ats_cap; > + > + if (!ats_cap || address < ats_cap) { > + return; > + } > + off = address - ats_cap; > + if (off >= PCI_EXT_CAP_ATS_SIZEOF) { > + return; > + } > + > + if (range_covers_byte(off, len, PCI_ATS_CTRL + 1)) { Do we really need +1 here? The rest looks good. Thanks > + if (dev->ats_ctrl_trigger) { > + dev->ats_ctrl_trigger(dev, !!(val & PCI_ATS_CTRL_ENABLE)); > + } > + } > +} > + > /* ACS (Access Control Services) */ > void pcie_acs_init(PCIDevice *dev, uint16_t offset) > { > diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h > index d3dd0f64b2..2bb1d68f3b 100644 > --- a/include/hw/pci/pci_device.h > +++ b/include/hw/pci/pci_device.h > @@ -160,6 +160,9 @@ struct PCIDevice { > /* ID of standby device in net_failover pair */ > char *failover_pair_id; > uint32_t acpi_index; > + > + /* PCI ATS enable/disable trigger */ > + void (*ats_ctrl_trigger)(PCIDevice *dev, bool enable); > }; > > static inline int pci_intx(PCIDevice *pci_dev) > diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h > index 798a262a0a..5f2dbd87cf 100644 > --- a/include/hw/pci/pcie.h > +++ b/include/hw/pci/pcie.h > @@ -154,4 +154,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, > Error **errp); > void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, > DeviceState *dev, Error **errp); > + > +void pcie_ats_config_write(PCIDevice *dev, uint32_t address, uint32_t val, > + int len); > + > #endif /* QEMU_PCIE_H */