From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkIUu-0003UH-Kt for qemu-devel@nongnu.org; Wed, 14 Sep 2016 18:17:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkIUp-0004D2-K4 for qemu-devel@nongnu.org; Wed, 14 Sep 2016 18:17:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44596) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkIUp-0004Cp-BQ for qemu-devel@nongnu.org; Wed, 14 Sep 2016 18:17:35 -0400 References: <147377800565.11859.4411044563640180545.stgit@brijesh-build-machine> <147377816100.11859.1924921034992764815.stgit@brijesh-build-machine> <1911fbd8-4476-c733-2972-0210a0afff80@redhat.com> <98729cf1-34ab-f0dd-7961-5e5efa2380b0@amd.com> <362908f3-69dc-5b8f-5976-95aba035f7c6@redhat.com> <269e58f7-6df3-6f84-a737-b7f441b0fa52@amd.com> <90efced4-3a77-d28b-e1fe-5a937bcf991b@redhat.com> <44c5f5f1-4697-6adb-4f4f-7203398bdd3b@amd.com> From: Paolo Bonzini Message-ID: Date: Thu, 15 Sep 2016 00:17:04 +0200 MIME-Version: 1.0 In-Reply-To: <44c5f5f1-4697-6adb-4f4f-7203398bdd3b@amd.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC PATCH v1 15/22] i386: sev: register RAM read/write ops for BIOS and PC.RAM region List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Brijesh Singh , ehabkost@redhat.com, crosthwaite.peter@gmail.com, armbru@redhat.com, mst@redhat.com, p.fedin@samsung.com, qemu-devel@nongnu.org, lcapitulino@redhat.com, rth@twiddle.net On 15/09/2016 00:06, Brijesh Singh wrote: >=20 > here is what I see: >=20 > int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, > uint8_t *buf, int len, int is_write) > { > ............ >=20 > if (is_write) > cpu_physical_memory_write_rom_internal() > else > address_space_rw() >=20 > ..... >=20 > } >=20 > So looking at code, i have impression that write will go through the > cpu_physical_memory_write_rom but the read will still go through > address_space_rw which will eventually invoke address_space_read. Yes, you'd have to modify it a bit. Something like diff --git a/exec.c b/exec.c index c8389f9..9fc9cef 100644 --- a/exec.c +++ b/exec.c @@ -2689,7 +2689,7 @@ enum write_rom_type { FLUSH_CACHE, }; =20 -static inline void cpu_physical_memory_write_rom_internal(AddressSpace *= as, +static inline void cpu_physical_memory_rw_debug_internal(AddressSpace *a= s, hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) { hwaddr l; @@ -2705,12 +2705,24 @@ static inline void cpu_physical_memory_write_rom_= internal(AddressSpace *as, if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { l =3D memory_access_size(mr, l, addr1); + /* Pass MMIO down to address_space_rw. */ + switch (type) { + case READ_DATA: + case WRITE_DATA: + /* ... set debug in attrs (not necessary anymore perhaps= ?) */ + address_space_rw(as, addr, attrs, buf, l, type =3D=3D WR= ITE_DATA); + break; + case FLUSH_CACHE: + break; + } } else { /* ROM/RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (type) { + case READ_DATA: + /* ... call hook ... */ case WRITE_DATA: - memcpy(ptr, buf, l); + /* ... call hook ... */ invalidate_and_set_dirty(mr, addr1, l); break; case FLUSH_CACHE: @@ -2729,7 +2739,7 @@ static inline void cpu_physical_memory_write_rom_in= ternal(AddressSpace *as, void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, const uint8_t *buf, int len) { - cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DAT= A); + cpu_physical_memory_rw_debug_internal(as, addr, buf, len, WRITE_DATA= ); } =20 void cpu_flush_icache_range(hwaddr start, int len) @@ -2744,8 +2754,8 @@ void cpu_flush_icache_range(hwaddr start, int len) return; } =20 - cpu_physical_memory_write_rom_internal(&address_space_memory, - start, NULL, len, FLUSH_CACHE= ); + cpu_physical_memory_rw_debug_internal(&address_space_memory, + start, NULL, len, FLUSH_CACHE)= ; } =20 typedef struct { @@ -3568,6 +3578,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong= addr, int l; hwaddr phys_addr; target_ulong page; + int mode =3D is_write ? WRITE_DATA : READ_DATA; =20 while (len > 0) { int asidx; @@ -3583,14 +3594,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulon= g addr, if (l > len) l =3D len; phys_addr +=3D (addr & ~TARGET_PAGE_MASK); - if (is_write) { - cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, - phys_addr, buf, l); - } else { - address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, - MEMTXATTRS_UNSPECIFIED, - buf, l, 0); - } + cpu_physical_memory_rw_debug_internal(cpu->cpu_ases[asidx].as, + phys_addr, buf, l, + mode); len -=3D l; buf +=3D l; addr +=3D l;