From: "Cédric Le Goater" <clg@kaod.org>
To: Andrew Jeffery <andrew@codeconstruct.com.au>,
Coco Li <lixiaoyan@google.com>, <peter.maydell@linaro.org>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>, <flwu@google.com>,
<philmd@linaro.org>
Subject: Re: [PATCH v2 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis
Date: Fri, 17 Oct 2025 07:31:39 +0200 [thread overview]
Message-ID: <f1bd1978-2f2f-4df3-9a09-77e15ccb46cf@kaod.org> (raw)
In-Reply-To: <dbd7c26cf0a77545bffaccaed7c9a364f97ac7af.camel@codeconstruct.com.au>
On 10/17/25 00:56, Andrew Jeffery wrote:
> On Wed, 2025-10-15 at 01:18 +0000, Coco Li wrote:
>> From: Felix Wu <flwu@google.com>
>>
>> Added 32 bits property for ASPEED GPIO. Previously it can only be access in bitwise manner.
>>
>> The changes to qobject is to index gpios with array indices on top of accessing with registers.
>> This allows for easier gpio access, especially in tests with complex behaviors that requires large number of gpios at a time, like fault injection and networking behaviors.
>>
>> Indexing multiple gpios at once allows qmp/side band client to no longer hardcode and populate register names and manipulate them faster.
>>
>> Signed-off-by: Felix Wu <flwu@google.com>
>
> Thanks for updating the commit message. It should be properly wrapped,
> but I expect that can be done when the patch is applied.
>
> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
yeah. I can do that.
Thanks,
C.
next prev parent reply other threads:[~2025-10-17 5:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 1:18 [PATCH v2 0/5] Add Aspeed GPIO test and Support Nuvoton Serial GPIO Expansion (SGPIO) device Coco Li
2025-10-15 1:18 ` [PATCH v2 1/5] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Coco Li
2025-10-16 22:56 ` Andrew Jeffery
2025-10-17 5:31 ` Cédric Le Goater [this message]
2025-10-15 1:18 ` [PATCH v2 2/5] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Coco Li
2025-10-17 5:37 ` Cédric Le Goater
2025-10-15 1:18 ` [PATCH v2 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs Coco Li
2025-10-15 1:18 ` [PATCH v2 4/5] hw/gpio/npcm8xx: Implement SIOX (SPGIO) device for NPCM without input pin logic Coco Li
2025-10-15 1:18 ` [PATCH v2 5/5] hw/gpio/npcm8xx: Implement npcm sgpio device " Coco Li
2025-10-17 5:49 ` [PATCH v2 0/5] Add Aspeed GPIO test and Support Nuvoton Serial GPIO Expansion (SGPIO) device Cédric Le Goater
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