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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 01/11] target/arm: Pass in pc to thumb_insn_is_16bit
Date: Thu, 8 Aug 2019 07:47:38 +0200	[thread overview]
Message-ID: <f1eaba6a-6f7d-b37d-52d5-88f16dbaf871@redhat.com> (raw)
In-Reply-To: <20190807045335.1361-2-richard.henderson@linaro.org>

On 8/7/19 6:53 AM, Richard Henderson wrote:
> This function is used in two different contexts, and it will be
> clearer if the function is given the address to which it applies.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  target/arm/translate.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 7853462b21..1f15f14022 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -9261,11 +9261,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
>      }
>  }
>  
> -static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
> +static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
>  {
> -    /* Return true if this is a 16 bit instruction. We must be precise
> -     * about this (matching the decode).  We assume that s->pc still
> -     * points to the first 16 bits of the insn.
> +    /*
> +     * Return true if this is a 16 bit instruction. We must be precise
> +     * about this (matching the decode).
>       */
>      if ((insn >> 11) < 0x1d) {
>          /* Definitely a 16-bit instruction */
> @@ -9285,7 +9285,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
>          return false;
>      }
>  
> -    if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
> +    if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
>          /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
>           * is not on the next page; we merge this into a 32-bit
>           * insn.
> @@ -11824,7 +11824,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
>       */
>      uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
>  
> -    return !thumb_insn_is_16bit(s, insn);
> +    return !thumb_insn_is_16bit(s, s->pc, insn);
>  }
>  
>  static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> @@ -12122,7 +12122,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>      }
>  
>      insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
> -    is_16bit = thumb_insn_is_16bit(dc, insn);
> +    is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
>      dc->pc += 2;
>      if (!is_16bit) {
>          uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
> 


  reply	other threads:[~2019-08-08  5:48 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-07  4:53 [Qemu-devel] [PATCH 00/11] target/arm: decodetree prep patches Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 01/11] target/arm: Pass in pc to thumb_insn_is_16bit Richard Henderson
2019-08-08  5:47   ` Philippe Mathieu-Daudé [this message]
2019-08-07  4:53 ` [Qemu-devel] [PATCH 02/11] target/arm: Introduce pc_curr Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 03/11] target/arm: Introduce read_pc Richard Henderson
2019-08-07 17:27   ` Peter Maydell
2019-08-07 18:04     ` Richard Henderson
2019-08-07 18:16       ` Peter Maydell
2019-08-07 18:25         ` Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 04/11] target/arm: Introduce add_reg_for_lit Richard Henderson
2019-08-08  5:43   ` Philippe Mathieu-Daudé
2019-08-07  4:53 ` [Qemu-devel] [PATCH 05/11] target/arm: Remove redundant s->pc & ~1 Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 06/11] target/arm: Replace s->pc with s->base.pc_next Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 07/11] target/arm: Replace offset with pc in gen_exception_insn Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 08/11] target/arm: Replace offset with pc in gen_exception_internal_insn Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 09/11] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
2019-08-07  4:53 ` [Qemu-devel] [PATCH 10/11] target/arm: Use unallocated_encoding for aarch32 Richard Henderson
2019-08-07 17:35   ` Philippe Mathieu-Daudé
2019-08-26  8:45   ` [Qemu-devel] [Qemu-arm] " Laurent Desnogues
2019-08-07  4:53 ` [Qemu-devel] [PATCH 11/11] target/arm: Remove helper_double_saturate Richard Henderson
2019-08-07 17:52 ` [Qemu-devel] [PATCH 00/11] target/arm: decodetree prep patches Peter Maydell
2019-08-09 12:49   ` Peter Maydell

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