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[83.51.160.214]) by smtp.gmail.com with ESMTPSA id g7sm2085858wmg.8.2019.08.07.22.47.38 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 22:47:39 -0700 (PDT) To: Richard Henderson , qemu-devel@nongnu.org References: <20190807045335.1361-1-richard.henderson@linaro.org> <20190807045335.1361-2-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Thu, 8 Aug 2019 07:47:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190807045335.1361-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.67 Subject: Re: [Qemu-devel] [PATCH 01/11] target/arm: Pass in pc to thumb_insn_is_16bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/7/19 6:53 AM, Richard Henderson wrote: > This function is used in two different contexts, and it will be > clearer if the function is given the address to which it applies. > > Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé > --- > target/arm/translate.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 7853462b21..1f15f14022 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -9261,11 +9261,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) > } > } > > -static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) > +static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) > { > - /* Return true if this is a 16 bit instruction. We must be precise > - * about this (matching the decode). We assume that s->pc still > - * points to the first 16 bits of the insn. > + /* > + * Return true if this is a 16 bit instruction. We must be precise > + * about this (matching the decode). > */ > if ((insn >> 11) < 0x1d) { > /* Definitely a 16-bit instruction */ > @@ -9285,7 +9285,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) > return false; > } > > - if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) { > + if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) { > /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix > * is not on the next page; we merge this into a 32-bit > * insn. > @@ -11824,7 +11824,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) > */ > uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b); > > - return !thumb_insn_is_16bit(s, insn); > + return !thumb_insn_is_16bit(s, s->pc, insn); > } > > static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > @@ -12122,7 +12122,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > } > > insn = arm_lduw_code(env, dc->pc, dc->sctlr_b); > - is_16bit = thumb_insn_is_16bit(dc, insn); > + is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn); > dc->pc += 2; > if (!is_16bit) { > uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b); >