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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id u13sm22953962wru.88.2020.03.30.09.21.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Mar 2020 09:21:01 -0700 (PDT) Subject: Re: [PATCH-for-5.0] gdbstub: Use correct address space with Qqemu.PhyMemMode packet To: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20200330153016.2959-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Mon, 30 Mar 2020 18:21:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Jon Doron , QEMU Developers , Alistair Francis , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Luc Michel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/30/20 6:08 PM, Peter Maydell wrote: > On Mon, 30 Mar 2020 at 16:30, Philippe Mathieu-Daud=C3=A9 wrote: >> >> Since commit 3f940dc98, we added support for vAttach packet >> to select a particular thread/cpu/core. However when using >> the GDB physical memory mode, it is not clear which CPU >> address space is used. >> Since the CPU address space is stored in CPUState::as, use >> address_space_rw() instead of cpu_physical_memory_rw(). >> >> Fixes: ab4752ec8d9 >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> gdbstub.c | 7 ++----- >> 1 file changed, 2 insertions(+), 5 deletions(-) >> >> diff --git a/gdbstub.c b/gdbstub.c >> index 013fb1ac0f..3baaef50e3 100644 >> --- a/gdbstub.c >> +++ b/gdbstub.c >> @@ -69,11 +69,8 @@ static inline int target_memory_rw_debug(CPUState *cp= u, target_ulong addr, >> >> #ifndef CONFIG_USER_ONLY >> if (phy_memory_mode) { >> - if (is_write) { >> - cpu_physical_memory_write(addr, buf, len); >> - } else { >> - cpu_physical_memory_read(addr, buf, len); >> - } >> + address_space_rw(cpu->as, addr, MEMTXATTRS_UNSPECIFIED, >> + buf, len, is_write); >> return 0; >=20 > There's an argument here for using > int asidx =3D cpu_asidx_from_attrs(cpu, MEMTXATTRS_UNSPECIFIED); > AddressSpace *as =3D cpu_get_address_space(cpu, asidx); >=20 > though it will effectively boil down to the same thing in the end > as there's no way for the gdbstub to specify whether it wanted > eg the Arm secure or non-secure physical address space. https://static.docs.arm.com/ihi0074/a/debug_interface_v6_0_architecture_spe= cification_IHI0074A.pdf * Configuration of hypervisor noninvasive debug. This field can have one of the following values: - 0b00 Separate controls for hypervisor noninvasive debug are not implemented,=20 or no hypervisor is implemented. For ARMv7 PEs that implement the=20 Virtualization Extensions, and for ARMv8 PEs that implement EL2, if=20 separate controls for hypervisor debug visibility are not implemented,=20 the hypervisor debug visibility is indicated by the relevant Non-secure=20 debug visibility fields NSNID and NSID. OK so for ARM "noninvasive debug is not implemented" and we would use=20 the core secure address space? Instead of MEMTXATTRS_UNSPECIFIED I should use a crafted MemTxAttrs with=20 .secure =3D 1, .unspecified =3D 1? The idea of this command is to use the= =20 CPU AS but not the MMU/MPU, maybe it doesn't make sense...