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Thu, 15 May 2025 15:28:31 +0000 (GMT) Message-ID: Date: Thu, 15 May 2025 10:28:30 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 39/50] ppc/xive: Assert group interrupts were redistributed To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-40-npiggin@gmail.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250512031100.439842-40-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=IqAecK/g c=1 sm=1 tr=0 ts=68260822 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=QkMIsaPlGapj7avH3-UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: QdpGJAUNCYqmCzo5vEqHYaWCEOxbi6O- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1MCBTYWx0ZWRfX3Y4BSm+2vXuK 3MzA4bxJUpQ4T/hc3qn5tvTAmleebLgnTcHm9WL2qyhR7g5gqjIhfRATBbINrAwb6kWerTysIhs k0wyIDVHPpN6wVqh3xxmCjheY/MCTAVriPab0UKY+nM2bvkP5d4KkwCrnkW7mY3O/sgOgBkIKCD dRMmFQ7xKFSsZEsW2VfWvCqRAQDr2eyv0vhpQy8MJ0/mMgrPHPeGOIECAmbE5ARrxgOGAyFGLgg gE1f/wCxE28QlS8BPW9G/4sgE6jaKIaQS0ZdRgj4EFJAblMxU/BE0Oan3q/tu0GSfqos3stcl01 YR3pLHPFi/s/xnEPQkZiNRa9+4Kdovq2wtDujiEJ2TimDy5GZlQHc0D/lM9UAoJcjpmofYBMlGc u7HjIl6o4i9o6S+P5kPWILUqX7w/4afTx0sOyB5kKVKLxS6aZYTdT1iDhSpbDSAEpDz5cT5K X-Proofpoint-GUID: qxb_YebHHvj0rYw3g-TuqCnjnqn9O5Xp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 spamscore=0 mlxlogscore=540 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150150 Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/2025 10:10 PM, Nicholas Piggin wrote: > Add some assertions to try to ensure presented group interrupts do > not get lost without being redistributed, if they become precluded > by CPPR or preempted by a higher priority interrupt. Reviewed-by: Michael Kowal Thanks,  MAK > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 2 ++ > hw/intc/xive2.c | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 4659821d4a..81af59f0ec 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -132,6 +132,8 @@ void xive_tctx_pipr_set(XiveTCTX *tctx, uint8_t ring, uint8_t pipr, > uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring); > uint8_t *regs = &tctx->regs[ring]; > > + g_assert(!xive_nsr_indicates_group_exception(ring, sig_regs[TM_NSR])); > + > sig_regs[TM_PIPR] = pipr; > > if (pipr < sig_regs[TM_CPPR]) { > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index ace5871706..e3060810d3 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -1089,6 +1089,7 @@ static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) > int rc; > > g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS); > + g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR])); > > /* > * Recompute the PIPR based on local pending interrupts. It will