Re: [PATCH v4 01/11] ppc: Add Power11 DD2.0 processor

[Harsh Prateek Bora <harshpb@linux.ibm.com>]

Hi Aditya,

On 5/28/24 12:35, Aditya Gupta wrote:
> Add CPU target code to add support for new Power11 Processor.
> 
> Power11 core is same as Power10, hence reuse functions defined for
> Power10.
> 
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
>   target/ppc/compat.c     |   7 +++
>   target/ppc/cpu-models.c |   3 ++
>   target/ppc/cpu-models.h |   3 ++
>   target/ppc/cpu_init.c   | 102 ++++++++++++++++++++++++++++++++++++++++
>   4 files changed, 115 insertions(+)
> 
> diff --git a/target/ppc/compat.c b/target/ppc/compat.c
> index ebef2cccecf3..12dd8ae290ca 100644
> --- a/target/ppc/compat.c
> +++ b/target/ppc/compat.c
> @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
>           .pcr_level = PCR_COMPAT_3_10,
>           .max_vthreads = 8,
>       },
> +    { /* POWER11, ISA3.10 */
> +        .name = "power11",
> +        .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS,
> +        .pcr = PCR_COMPAT_3_10,
> +        .pcr_level = PCR_COMPAT_3_10,
> +        .max_vthreads = 8,
> +    },
>   };
>   
>   static const CompatInfo *compat_by_pvr(uint32_t pvr)
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index f2301b43f78b..ece348178188 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -734,6 +734,8 @@
>                   "POWER9 v2.2")
>       POWERPC_DEF("power10_v2.0",  CPU_POWERPC_POWER10_DD20,           POWER10,
>                   "POWER10 v2.0")
> +    POWERPC_DEF("power11_v2.0",  CPU_POWERPC_POWER11_DD20,           POWER11,
> +                "POWER11_v2.0")
>   #endif /* defined (TARGET_PPC64) */
>   
>   /***************************************************************************/
> @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>       { "power8nvl", "power8nvl_v1.0" },
>       { "power9", "power9_v2.2" },
>       { "power10", "power10_v2.0" },
> +    { "power11", "power11_v2.0" },
>   #endif
>   
>       /* Generic PowerPCs */
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index 0229ef3a9a5c..ef74e387b047 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -354,6 +354,8 @@ enum {
>       CPU_POWERPC_POWER10_BASE       = 0x00800000,
>       CPU_POWERPC_POWER10_DD1        = 0x00801100,
>       CPU_POWERPC_POWER10_DD20       = 0x00801200,
> +    CPU_POWERPC_POWER11_BASE       = 0x00820000,
> +    CPU_POWERPC_POWER11_DD20       = 0x00821200,
>       CPU_POWERPC_970_v22            = 0x00390202,
>       CPU_POWERPC_970FX_v10          = 0x00391100,
>       CPU_POWERPC_970FX_v20          = 0x003C0200,
> @@ -391,6 +393,7 @@ enum {
>       CPU_POWERPC_LOGICAL_2_07       = 0x0F000004,
>       CPU_POWERPC_LOGICAL_3_00       = 0x0F000005,
>       CPU_POWERPC_LOGICAL_3_10       = 0x0F000006,
> +    CPU_POWERPC_LOGICAL_3_10_PLUS  = 0x0F000007,
>   };
>   
>   /* System version register (used on MPC 8xxx)                                */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 01e358a4a5ac..82d700382cdd 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6763,6 +6763,108 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>       pcc->l1_icache_size = 0x8000;
>   }
>   
> +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
> +{
> +    uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
> +    uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
> +
> +    if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
> +        return true;
> +    }
> +
> +    if (base != pcc_base) {
> +        return false;
> +    }
> +
> +    if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
> +        return true;
> +    }
> +
> +    return false;
> +}
> +
> +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +
> +    dc->fw_name = "PowerPC,POWER11";
> +    dc->desc = "POWER11";
> +    pcc->pvr_match = ppc_pvr_match_power11;
> +    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
> +                    PCR_COMPAT_3_00;
> +    pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
> +                         PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> +    pcc->init_proc = init_proc_POWER10;
> +    pcc->check_pow = check_pow_nocheck;
> +    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> +                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> +                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> +                       PPC_FLOAT_FRSQRTES |
> +                       PPC_FLOAT_STFIWX |
> +                       PPC_FLOAT_EXT |
> +                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> +                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
> +                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> +                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
> +                       PPC_SEGMENT_64B | PPC_SLBI |
> +                       PPC_POPCNTB | PPC_POPCNTWD |
> +                       PPC_CILDST;
> +    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> +                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
> +                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> +                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> +                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> +                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> +                        PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
> +                        PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
> +    pcc->msr_mask = (1ull << MSR_SF) |
> +                    (1ull << MSR_HV) |
> +                    (1ull << MSR_TM) |
> +                    (1ull << MSR_VR) |
> +                    (1ull << MSR_VSX) |
> +                    (1ull << MSR_EE) |
> +                    (1ull << MSR_PR) |
> +                    (1ull << MSR_FP) |
> +                    (1ull << MSR_ME) |
> +                    (1ull << MSR_FE0) |
> +                    (1ull << MSR_SE) |
> +                    (1ull << MSR_DE) |
> +                    (1ull << MSR_FE1) |
> +                    (1ull << MSR_IR) |
> +                    (1ull << MSR_DR) |
> +                    (1ull << MSR_PMM) |
> +                    (1ull << MSR_RI) |
> +                    (1ull << MSR_LE);
> +    pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> +        (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> +        LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> +        (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> +                             LPCR_DEE | LPCR_OEE))
> +        | LPCR_MER | LPCR_GTSE | LPCR_TC |
> +        LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> +    /* DD2 adds an extra HAIL bit */
> +    pcc->lpcr_mask |= LPCR_HAIL;
> +

I had posted a patch to get rid of this growing code duplication here:
https://lore.kernel.org/qemu-devel/20240523051412.226970-8-harshpb@linux.ibm.com/

Would you mind considering the relevant patches to rebase your changes?

regards,
Harsh

> +    pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> +    pcc->mmu_model = POWERPC_MMU_3_00;
> +#if !defined(CONFIG_USER_ONLY)
> +    /* segment page size remain the same */
> +    pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> +    pcc->radix_page_info = &POWER10_radix_page_info;
> +    pcc->lrg_decr_bits = 56;
> +#endif
> +    pcc->excp_model = POWERPC_EXCP_POWER10;
> +    pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
> +    pcc->bfd_mach = bfd_mach_ppc64;
> +    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> +                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> +                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
> +                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
> +    pcc->l1_dcache_size = 0x8000;
> +    pcc->l1_icache_size = 0x8000;
> +}
> +
>   #if !defined(CONFIG_USER_ONLY)
>   void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
>   {