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From: Eric Auger <eric.auger@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Mostafa Saleh <smostafa@google.com>
Subject: Re: [PATCH 3/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
Date: Tue, 26 Sep 2023 17:39:12 +0200	[thread overview]
Message-ID: <f254b6e5-f02a-5781-570a-2c9688667b36@redhat.com> (raw)
In-Reply-To: <20230914145705.1648377-4-peter.maydell@linaro.org>

Hi Peter,

On 9/14/23 16:57, Peter Maydell wrote:
> The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
> supported, so we should theoretically have implemented it as part of
> the recent S2P work.  Fortunately, for us the implementation is a
> no-op.
>
> This feature is about interpretation of the stage 2 page table
> descriptor XN bits, which control execute permissions.
>
> For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
> IOMMUAccessFlags) only indicate read and write; we do not distinguish
> data reads from instruction reads outside the CPU proper.  In the
> SMMU architecture's terms, our interconnect between the client device
> and the SMMU doesn't have the ability to convey the INST attribute,
> and we therefore use the default value of "data" for this attribute.
>
> We also do not support the bits in the Stream Table Entry that can
> override the on-the-bus transaction attribute permissions (we do not
> set SMMU_IDR1.ATTR_PERMS_OVR=1).
you may precise it is called INSTCFG
>
> These two things together mean that for our implementation, it never
> has to deal with transactions with the INST attribute, and so it can
> correctly ignore the XN bits entirely.  So we already implement
> FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
> that we need to.
>
> Advertise the presence of the feature in SMMU_IDR3.XNX.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  hw/arm/smmuv3.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 94d388fc950..d9e639f7c41 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -279,6 +279,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
>      s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS,   SMMU_CMDQS);
>  
>      s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
> +    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1);
>      s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
>      s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
>  
With Mostafa's suggestion
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric



  parent reply	other threads:[~2023-09-26 15:39 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-14 14:57 [PATCH 0/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX Peter Maydell
2023-09-14 14:57 ` [PATCH 1/3] hw/arm/smmuv3: Update ID register bit field definitions Peter Maydell
2023-09-26 15:22   ` Eric Auger
2023-09-14 14:57 ` [PATCH 2/3] hw/arm/smmuv3: Sort ID register setting into field order Peter Maydell
2023-09-26 15:29   ` Eric Auger
2023-09-14 14:57 ` [PATCH 3/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature Peter Maydell
2023-09-22 10:34   ` Mostafa Saleh
2023-09-22 10:54     ` Peter Maydell
2023-09-22 13:39       ` Mostafa Saleh
2023-09-26 15:39   ` Eric Auger [this message]
2023-09-14 15:53 ` [PATCH 0/3] hw/arm/smmuv3: Advertise SMMUv3.1-XNX Richard Henderson
2023-09-22 10:41 ` Mostafa Saleh

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